System and method to read and write data a magnetic tunnel junction element

• US 8,130,534 B2
• Filed: 01/08/2009
• Issued: 03/06/2012
• Est. Priority Date: 01/08/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Abu-Rahma, Mohamed Hassan, Song, Seung-Chul, Yoon, Sei Seung, Park, Dongkyu, Zhong, Cheng, Davierwalla, Anosh B.
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): TRAN, ANTHAN
• Application Number:
  US12/350,304
• Publication Number:
  US 20100172173A1
• Time in Patent Office: 1,153 Days
• Field of Search: 365/154, 365/158, 365/148
• US Class Current: 365/158
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled to the STT-MTJ element.

Claims

1. A device comprising:

a spin transfer torque (STT) magnetic tunnel junction (MTJ) element; and

a transistor coupled to the STT-MTJ element,

wherein the transistor includes a first gate and a second gate, wherein the STT-MTJ element is within a memory cell in a memory array, wherein the first gate is coupled to a word line of the memory array, and wherein the second gate is coupled to a write enable line of the memory array.

2. The device of claim 1, wherein the STT-MTJ element comprises:

a free magnetic layer;

a tunnel barrier; and

a pinned magnetic layer;

wherein a data value stored at the STT-MTJ element is determined by a direction of a write current though the tunnel barrier.

3. The device of claim 2, wherein the first gate and the second gate are independently biasable.

4. The device of claim 1, wherein a read path includes an inversion channel corresponding to the first gate.

5. The device of claim 4, wherein the first gate limits a maximum current to not exceed a critical disturbance current value of the STT-MTJ element.

6. The device of claim 5, wherein a first threshold voltage of the first gate is different from a second threshold voltage of the second gate.

7. The device of claim 6, wherein the transistor is an independent gate “

fin”

Field Effect Transistor (IG-FinFET).

8. The device of claim 1, wherein the transistor defines a read path and a write path for the STT-MTJ element, and wherein the read path and the write path are decoupled by the first gate and the second gate.

9. The device of claim 8, wherein the second gate is coupled to gates of multiple memory cells in a column of the memory array.

10. A device comprising:

as in transfer torque (STT) magnetic tunnel junction (MTJ) element; and

a transistor coupled to the STT-MTJ element,

wherein the transistor includes a first gate and a second gate, wherein a first signal applied to the second gate enables a data write at the STT-MTJ element, and wherein a second signal applied to the second gate disables a data write at the STT-MTJ element.

11. The device of claim 10, wherein the first gate has an inversion channel, and wherein a read path includes the inversion channel.

12. The device of claim 11, wherein the first gate limits a maximum current to not exceed a critical disturbance current value of the STT-MTJ element.

13. The device of claim 12, wherein a first threshold voltage of the first gate is different from a second threshold voltage of the second gate.

14. The device of claim 13, wherein the transistor is an independent gate “

fin”

Field-Effect Transistor (IG-FinFET).

15. A memory comprising:

an array of memory cells, the array including a plurality of columns, each memory cell in the array of memory cells including a magnetic tunnel junction (MTJ) device coupled to a dual-gate transistor, the dual-gate transistor having a first gate coupled to a word line of a plurality of word lines and having a second gate coupled to a write enable line of a plurality of write enable lines;

wherein at least one column of the plurality of columns is controllable by the write enable line during a write operation.

16. The memory of claim 15, wherein the memory array includes a plurality of rows, and wherein at least one row of the plurality of rows is controllable by the word line during a read operation.

17. The memory of claim 15, wherein the memory array includes a plurality of rows, and wherein a particular row of the memory array is addressable via a particular word line.

18. The memory of claim 15, wherein a read operation is performed by biasing the write enable line and the word line to enable a read current and not a write current through the MTJ device.

19. The memory of claim 15, wherein at least one unselected word line of the plurality of word lines in the memory array is set to a negative value during a write operation.

20. The memory of claim 15, wherein the first gate is biased at a logical high level and the second gate is biased at a logical low level to read data.

21. A device comprising:

a magnetic tunnel junction (MTJ) element; and

a common portion of a read/write data path that includes a transistor coupled to the MTJ element,

wherein the transistor includes a first gate and a second gate, wherein the first gate is coupled to a word line, and wherein the second gate is coupled to a write enable line.

22. The device of claim 21, wherein the first gate is active during a read operation, and wherein both the first gate and the second gates are active during a write operation.

23. A method for storing data in a spin-torque transfer magnetoresistive random access memory (STT-MRAM), the method comprising:

writing data into a magnetic tunnel junction (MTJ) element; and

reading data out of the MTJ element;

wherein the MTJ element is coupled to a transistor, wherein the transistor includes a first gate and a second gate, wherein writing data into the MTJ element uses a data write path, wherein reading data out of the MTJ element uses a data read path, wherein the data write path and the data read path are different paths, and wherein the first gate of the transistor and the second gate of the transistor decouple the data write path and the data read path.

24. The method of claim 23, wherein the second gate is biased to disable a write current during a data read operation.

25. The method of claim 24, wherein the second gate is biased to enable a write current during a data write operation.