JTAG debug test system adapter with three sets of leads
First Claim
1. A debug test system adapter comprising:
- A. a first set of leads including;
i. a clock input and output lead,ii. a mode input and output lead,iii. a test in data output lead, andiv. a test out data input lead;
B. a second set of leads including;
i. a test clock input lead carrying a test clock signal coupled to the clock input and output lead,ii. a test mode select input lead carrying a test mode select signal coupled to the mode input and output lead,iii. a test in data input lead carrying a test in data signal selectively coupled to the test in data output lead and the mode input and output lead, andiv. a test out data output lead carrying a test out data signal selectively coupled to the test out data input lead and the mode input and output lead; and
C. a third set of leads including first and second data transport leads selectively coupled with the mode input and output lead.
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Abstract
A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.
16 Citations
6 Claims
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1. A debug test system adapter comprising:
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A. a first set of leads including; i. a clock input and output lead, ii. a mode input and output lead, iii. a test in data output lead, and iv. a test out data input lead; B. a second set of leads including; i. a test clock input lead carrying a test clock signal coupled to the clock input and output lead, ii. a test mode select input lead carrying a test mode select signal coupled to the mode input and output lead, iii. a test in data input lead carrying a test in data signal selectively coupled to the test in data output lead and the mode input and output lead, and iv. a test out data output lead carrying a test out data signal selectively coupled to the test out data input lead and the mode input and output lead; and C. a third set of leads including first and second data transport leads selectively coupled with the mode input and output lead. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification