System and method for common history pessimism relief during static timing analysis

• US 8,141,014 B2
• Filed: 08/10/2009
• Issued: 03/20/2012
• Est. Priority Date: 08/10/2009
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: International Business Machines Corporation
• Inventors: Foreman, Eric A., Habitz, Peter A., Hathaway, David J., Hemmett, Jeffrey G., Kalafala, Kerim, Soreff, Jeffrey P.
• Primary Examiner(s): Lin, Sun
• Application Number:
  US12/538,229
• Publication Number:
  US 20110035714A1
• Time in Patent Office: 953 Days
• Field of Search: 716/108, 716/113, 716/136, 703/16
• US Class Current: 716/108
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A system and method for adjustment of modeled timing data variation as a function of past state and/or switching history during static timing analysis. One illustrative embodiment may include inputting and asserting at least one of initial signal history bound and explicit device history bound constraints for at least one signal of a circuit design and evaluating for a segment processed during a forward propagation of block based static timing analysis whether any input signal to a current segment has a bounded history, at least one of propagated and asserted. The method may further include evaluating for the segment whether history bounds are downstream from a gating restriction, and processing a next segment until there are no further segments.

Claims

1. A method for adjustment of modeled timing data variation as a function of a past state and/or a switching history during a static timing analysis performed by at least one computing device, the method comprising:

at least one of inputting and asserting at least one of an initial signal history bound constraint and an explicit device history bound constraint for at least one signal of a circuit design, using the at least one computing device;

evaluating for a segment processed during a forward propagation of a block based static timing analysis whether any input signal to a current segment has a bounded history, at least one of propagated and asserted;

evaluating for the segment whether history bounds are downstream from a gating restriction using the at least one computing device; and

processing a next segment until there are no further segments.

2. The method of claim 1, wherein in response to the current segment not having a bounded history, further comprising proceeding directly to the processing of the next segment.

3. The method of claim 2, further comprising performing a statistical static timing analysis (SSTA) slack evaluation.

4. The method of claim 3, wherein the SSTA slack evaluation includes processing history based parameters, wherein the history based parameters with common history bounds and gating restrictions are at least partially canceled during slack calculations.

5. The method of claim 1, wherein in response to the history bounds not being downstream from the gating restriction, further comprising propagating the history bounds without a gating restriction.

6. The method of claim 1, wherein in response to the history bounds being downstream from the gating restriction, further comprising propagating the history bounds with a gating restriction.

7. The method of claim 1, further comprising performing a generalized common path pessimism removal (gCPPR) processing.

8. The method of claim 7, wherein the gCPPR processing includes canceling at least a portion of a history component in a test where both sides of the test are found to share a common bound and gating restriction.

9. The method of claim 1, wherein the timing time data of the modeled timing data variation includes a delay value.

10. A program product stored on a non-transitory computer readable medium, which when executed by at least one computing device, causes the at least one computing device to adjust modeled timing data variation as a function of a past state and/or a switching history during a static timing analysis, the program product comprising:

program code for at least one of inputting and asserting at least one of an initial signal history bound constraint and an explicit device history bound constraint for at least one signal of a circuit design;

program code for evaluating for a segment processed during a forward propagation of a block based static timing analysis whether any input signal to a current segment has a bounded history, at least one of propagated and asserted;

program code for evaluating for the segment whether history bounds are downstream from a gating restriction; and

program code for processing a next segment until there are no further segments.

11. The program product of claim 10, further comprising program code for propagating the history bounds without a gating restriction in response to the history bounds not being downstream from the gating restriction.

12. The program product of claim 10, further comprising program code for proceeding directly to the processing of the next segment in response to the current segment not having a bounded history.

13. The program product of claim 10, further comprising program code for proceeding directly to the processing of the next segment in response to the current segment not having a bounded history.

14. The program product of claim 10, further comprising program code for propagating the history bounds with a gating restriction in response to the history bounds being downstream from the gating restriction.

15. The program product of claim 10, further comprising program code for performing a generalized common path pessimism removal (gCPPR) processing.

16. The program product of claim 15, wherein the program code for gCPPR processing includes program code for canceling at least a portion of a history component in a test where both sides of the test are found to share a common bound and gating restriction.

17. The program product of claim 10, further comprising program code for performing a statistical static timing analysis (SSTA) slack evaluation process.

18. The program product of claim 17, wherein the program code for the SSTA slack evaluation includes program code for processing history based parameters, wherein the history based parameters with common history bounds and gating restrictions are at least partially canceled during slack calculations.

19. The program product of claim 10, wherein the timing time data of the modeled timing data variation includes a delay value.

20. A system for adjustment of modeled timing data variation as a function of a past state and/or a switching history during static timing analysis, the system comprising:

a processor;

a memory; and

a static timing engine stored in the memory and operable to be executed by the processor, wherein the static timing engine is structured to perform;

at least one of inputting and asserting at least one of an initial signal history bound constraint and an explicit device history bound constraint for at least one signal of a circuit design;

evaluating for a segment processed during a forward propagation of a block based static timing analysis whether any input signal to a current segment has a bounded history, at least one of propagated and asserted;

evaluating for the segment whether history bounds are downstream from a gating restriction; and

processing a next segment until there are no further segments.

21. The system of claim 20, wherein the static timing engine is further structured to proceed directly to the processing of the next segment in response to the current segment not having a bounded history.

22. The system of claim 20, wherein the static timing engine is further structured to propagate the history bounds without a gating restriction in response to the history bounds are not downstream from the gating restriction.

23. The system of claim 20, wherein time data of the modeled timing data variation includes a delay value.