Computer memory architecture for hybrid serial and parallel computing systems
DC CAFCFirst Claim
1. An apparatus comprising:
- a serial processor to execute instructions in a computing program primarily in serial;
a first, private memory to store data solely for use by the serial processor in executing the instructions;
a plurality of parallel processors to execute instructions in the computing program primarily in parallel, at least one parallel processor of the plurality of parallel processors having a second, local read-only memory; and
a plurality of shared memory modules to store data for use by the plurality of parallel processors in executing the instructions.
0 Assignments
Litigations
2 Petitions
Accused Products
Abstract
In one embodiment, a serial processor is configured to execute software instructions in a software program in serial. A serial memory is configured to store data for use by the serial processor in executing the software instructions in serial. A plurality of parallel processors are configured to execute software instructions in the software program in parallel. A plurality of partitioned memory modules are provided and configured to store data for use by the plurality of parallel processors in executing software instructions in parallel. Accordingly, a processor/memory structure is provided that allows serial programs to use quick local serial memories and parallel programs to use partitioned parallel memories. The system may switch between a serial mode and a parallel mode. The system may incorporate pre-fetching commands of several varieties. For example, towards switching between the serial mode and the parallel mode, the serial processor is configured to send a signal to start pre-fetching of data from the shared memory.
5 Citations
38 Claims
-
1. An apparatus comprising:
-
a serial processor to execute instructions in a computing program primarily in serial; a first, private memory to store data solely for use by the serial processor in executing the instructions; a plurality of parallel processors to execute instructions in the computing program primarily in parallel, at least one parallel processor of the plurality of parallel processors having a second, local read-only memory; and a plurality of shared memory modules to store data for use by the plurality of parallel processors in executing the instructions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 31)
-
-
20. An apparatus comprising:
-
a serial processor to execute instructions in a computing program primarily in serial; a first, private memory to store data solely for use by the serial processor in executing the instructions; a plurality of parallel processors to execute instructions in the computing program primarily in parallel, at least one parallel processor of the plurality of parallel processors having a second, local read-only memory; and a plurality of shared memory modules to store data for use by the plurality of parallel processors in executing the instructions; wherein prior to a transition from a serial processing mode to a parallel processing mode, the serial processor is to broadcast a prefetching signal to the plurality of parallel processors to initiate prefetching of data from at least one of the plurality of shared memory modules. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
-
-
32. A method of transitioning between a serial processing mode and a parallel processing mode in a computing system, the method comprising:
-
while in the serial processing mode, transferring updated data from a first private serial memory of a serial processor to at least one shared memory module of a plurality of shared memory modules; receiving a corresponding acknowledgement from the at least one shared memory module that the updated data has been queued or committed for storage in memory, prior to any memory requests from a parallel processor of a plurality of parallel processors; and broadcasting a first signal to the plurality of parallel processors for substantially concurrent initiation of the parallel processing mode. - View Dependent Claims (33, 34, 35, 36, 37, 38)
-
Specification