Automatic defect management in memory devices

• US 8,151,163 B2
• Filed: 12/03/2007
• Issued: 04/03/2012
• Est. Priority Date: 12/03/2006
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Shalvi, Ofir, Sokolov, Dotan
• Primary Examiner(s): Abraham, Esaw
• Application Number:
  US11/995,812
• Publication Number:
  US 20100115376A1
• Time in Patent Office: 1,583 Days
• Field of Search: 714/709, 714/710, 714/718, 714/758, 714/763
• US Class Current: 714/758
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

A method for storing data in a memory (28) that includes analog memory cells (32) includes identifying one or more defective memory cells in a group of the analog memory cells. An Error Correction Code (ECC) is selected responsively to a characteristic of the identified defective memory cells. The data is encoded using the selected ECC and the encoded data is stored in the group of the analog memory cells. In an alternative method, an identification of one or more defective memory cells among the analog memory cells is generated. Analog values are read from the analog memory cells in which the encoded data were stored, including at least one of the defective memory cells. The analog values are processed using an ECC decoding process responsively to the identification of the at least one of the defective memory cells, so as to reconstruct the data.

Claims

1. A method for storing data in a memory that includes analog memory cells, comprising:

identifying one or more defective memory cells in a group of the analog memory cells;

selecting an Error Correction Code (ECC) responsively to a characteristic of the identified defective memory cells; and

encoding the data using the selected ECC and storing the encoded data in the group of the analog memory cells,

wherein identifying the defective cells comprises storing information related to the identified defective memory cells at a first time, and wherein selecting the ECC comprises retrieving the stored information, determining the characteristic based on the information and selecting the ECC at a second time subsequent to the first time.

2. The method according to claim 1, wherein the characteristic comprises a number of the defective memory cells in the group.

3. The method according to claim 1, wherein selecting the ECC comprises determining a redundancy level of the ECC based on the characteristic.

4. The method according to claim 1, wherein identifying the defective memory cells comprises identifying multiple sets of the defective memory cells in respective multiple groups of the memory cells, and wherein selecting the ECC comprises selecting multiple different ECCs for the multiple groups based on respective characteristics of the sets of the defective memory cells.

5. The method according to claim 1, wherein storing the information comprises updating the stored information at a third time subsequent to the first time.

6. The method according to claim 1, wherein storing the information comprises compressing the information and storing the compressed information.

7. The method according to claim 1, wherein storing the information comprises storing the information in the memory.

8. The method according to claim 1, wherein the data includes first and second groups of bits, and wherein selecting the ECC comprises selecting respective, different first and second ECCs for encoding the first and second groups of the bits.

9. The method according to claim 1, wherein identifying the defective cells comprises running a background task that identifies the cells.

10. The method according to claim 9, wherein running the background task comprises assessing a status of electrical power supplied to the memory, and selectively enabling the task responsively to the status.

11. A method for storing data in a memory that includes analog memory cells, comprising:

identifying one or more defective memory cells in a group of the analog memory cells;

selecting an Error Correction Code (ECC) responsively to a characteristic of the identified defective memory cells; and

encoding the data using the selected ECC and storing the encoded data in the group of the analog memory cells,

wherein selecting the ECC comprises partitioning the analog memory cells in the group into first and second subsets, substituting at least one of the defective memory cells with a respective at least one of the memory cells of the first subset, and storing the encoded data in the analog memory cells of the second subset.

12. The method according to claim 11, wherein selecting the ECC comprises selecting respective first and second sizes of the first and second subsets.

13. The method according to claim 11, wherein the memory is packaged in a device package, and wherein selecting the first and second sizes comprises selecting the sizes by logic that is coupled to the memory and packaged in the device package.

14. The method according to claim 11, wherein the memory has a configuration that imposes a constraint on substituting the defective memory cells, and wherein substituting the at least one of the defective memory cells comprises selecting the at least one of the defective memory cells responsively to the constraint.

15. The method according to claim 14, wherein the memory includes blocks of the memory cells that can only be substituted en-bloc.

16. The method according to claim 11, wherein partitioning the memory cells comprises defining multiple sets of the memory cells and allocating each of the sets to one of substitution of the at least one of the defective memory cells and storage of the encoded data.

17. A method for storing data in a memory that includes analog memory cells, comprising:

identifying one or more defective memory cells in a group of the analog memory cells;

selecting an Error Correction Code (ECC) responsively to a characteristic of the identified defective memory cells; and

encoding the data using the selected ECC and storing the encoded data in the group of the analog memory cells,

wherein encoding the data comprises encoding the data using a first ECC by a first controller and encoding the data using a second ECC by a second controller, and wherein selecting the ECC comprises assigning a first subset of the memory cells in the group for use by the first ECC and a second subset of the memory cells in the group for use by the second ECC.

18. The method according to claim 17, wherein the first controller and the memory are packaged in a single device, and wherein the second controller is external to the device.

19. The method according to claim 18, wherein assigning the first and second subsets comprises determining a size of the first subset responsively to the size of the second subset.

20. The method according to claim 18, wherein encoding the data comprises overwriting the data stored in at least some of the memory cells in the second subset with the first ECC, and, when retrieving the data by the second controller, regenerating the overwritten data by the first controller and sending the retrieved data together with the regenerated data to the second controller.

21. A data storage apparatus, comprising:

an interface, which is coupled to communicate with a memory that includes a plurality of analog memory cells; and

a processor, which is coupled to identify one or more defective memory cells in a group of the analog memory cells, to select an Error Correction Code (ECC) responsively to a characteristic of the identified defective memory cells, to encode the data using the selected ECC and to store the encoded data in the group of the analog memory cells,

wherein the processor is coupled to store information related to the identified defective memory cells at a first time, and to retrieve the stored information, determine the characteristic based on the information and select the ECC at a second time subsequent to the first time.

22. The apparatus according to claim 21, wherein the characteristic comprises a number of the defective memory cells in the group.

23. The apparatus according to claim 21, wherein the processor is coupled to determine a redundancy level of the ECC based on the characteristic.

24. The apparatus according to claim 21, wherein the processor is coupled to identify multiple sets of the defective memory cells in respective multiple groups of the memory cells, and to select multiple different ECCs for the multiple groups based on respective characteristics of the sets of the defective memory cells.

25. The apparatus according to claim 21, wherein the processor is coupled to update the stored information at a third time subsequent to the first time.

26. The apparatus according to claim 21, wherein the processor is coupled to compress the information and to store the compressed information.

27. The apparatus according to claim 21, wherein the processor is coupled to store the information in the memory.

28. The apparatus according to claim 21, wherein the data includes first and second groups of bits, and wherein the processor is coupled to select respective, different first and second ECCs for encoding the first and second groups of the bits.

29. The apparatus according to claim 21, wherein the processor is coupled to run a background task that identifies the defective cells.

30. The apparatus according to claim 29, wherein the processor is coupled to assess a status of electrical power supplied to the memory, and to selectively enable the task responsively to the status.

31. The apparatus according to claim 21, wherein the memory comprises multiple memory dies, and wherein the interface is coupled to communicate with the multiple memory dies.

32. A data storage apparatus, comprising:

an interface, which is coupled to communicate with a memory that includes a plurality of analog memory cells; and

a processor, which is coupled to identify one or more defective memory cells in a group of the analog memory cells, to select an Error Correction Code (ECC) responsively to a characteristic of the identified defective memory cells, to encode the data using the selected ECC and to store the encoded data in the group of the analog memory cells,

wherein the processor is coupled to partition the analog memory cells in the group into first and second subsets, to substitute at least one of the defective memory cells with a respective at least one of the memory cells of the first subset, and to store the encoded data in the analog memory cells of the second subset.

33. The apparatus according to claim 32, wherein the processor is coupled to select respective first and second sizes of the first and second subsets.

34. The apparatus according to claim 32, wherein the memory has a configuration that imposes a constraint on substituting the defective memory cells, and wherein the processor is coupled to select the at least one of the defective memory cells responsively to the constraint.

35. The apparatus according to claim 34, wherein the memory includes blocks of the memory cells that can only be substituted en-bloc.

36. The apparatus according to claim 32, wherein the processor is coupled to define multiple sets of the memory cells and to allocate each of the sets to one of substitution of the at least one of the defective memory cells and storage of the encoded data.

37. A data storage apparatus, comprising:

an interface, which is coupled to communicate with a memory that includes a plurality of analog memory cells; and

a processor, which is coupled to identify one or more defective memory cells in a group of the analog memory cells, to select an Error Correction Code (ECC) responsively to a characteristic of the identified defective memory cells, to encode the data using the selected ECC and to store the encoded data in the group of the analog memory cells,

wherein the data is further encoded using another ECC by another processor, and wherein the processor is coupled to assign a first subset of the memory cells in the group for use by the ECC and a second subset of the memory cells in the group for use by the other ECC.

38. The apparatus according to claim 37, wherein the processor and the memory are packaged in a single device, and wherein the other processor is external to the device.

39. The apparatus according to claim 38, wherein the processor is coupled to determine a size of the first subset responsively to the size of the second subset.

40. The apparatus according to claim 38, wherein the processor is coupled to overwrite the data stored in at least some of the memory cells in the second subset with the first ECC, and, when retrieving the data by the other processor, regenerating the overwritten data by the processor and sending the retrieved data together with the regenerated data to the other processor.

41. A data storage apparatus, comprising:

a memory, which comprises a plurality of analog memory cells; and

a processor, which is connected to the memory and is coupled to identify one or more defective memory cells in a group of the analog memory cells, to select an Error Correction Code (ECC) responsively to a characteristic of the identified defective memory cells, to encode the data using the selected ECC and to store the encoded data in the group of the analog memory cells,

and comprising logic circuitry, which is operative to partition the analog memory cells in the group into first and second subsets, to substitute at least one of the defective memory cells with a respective at least one of the memory cells of the first subset and to store the encoded data in the analog memory cells of the second subset, wherein the apparatus further comprises a package, which contains the memory and the logic circuitry.

42. The apparatus according to claim 41, wherein the logic circuitry is operative to select respective first and second sizes of the first and second subsets.