RFID device time synchronization from a public source

• US 8,154,407 B2
• Filed: 02/14/2011
• Issued: 04/10/2012
• Est. Priority Date: 11/19/2007
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Greeff, Roy, Smith, Freddie W., Ovard, David K.
• Primary Examiner(s): TRIEU, VAN THANH
• Application Number:
  US13/026,826
• Publication Number:
  US 20110133897A1
• Time in Patent Office: 421 Days
• Field of Search: 340/539.1, 340/539.11, 340/539.13, 340/572.1, 340/572.4, 340/572.7, 340/572.8, 340/10.1, 340/10.4, 342/357.09, 342/357.1, 342/386, 367/131, 367/149, 701/213, 701/214
• US Class Current: 340/572.4
• CPC Class Codes: G01D 9/005 Solid-state data loggers
• CPC Class Codes: G06K 19/0716 at least one of the integrated circuit chips comprising a sensor or an interface to a sensor
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card

Abstract

A radio frequency identification (RFID) device includes an antenna linked to a receiving circuit, the antenna tuned to receive a radio frequency (RF) time-code signal from a public source, a controller circuit and an internal clock linked to the receiving circuit, a microcontroller linked to the receiving circuit, a memory linked to the microcontroller, and a battery linked to and powering the receiving circuit, controller circuit, internal clock, microcontroller and memory.

Claims

1. A system comprising:

a radio frequency identification (RFID) device comprising;

an antenna tuned to receive a radio frequency (RF) position signal from a public source;

a receiving circuit linked to the antenna, wherein the receiving circuit is configured to convert the received RF position signal into a digital position bit stream;

a controller circuit linked to the receiving circuit, wherein the controller circuit is configured to decode the digital position bit stream; and

an internal clock linked to the controller circuit, wherein a time maintained by the internal clock is updated based on the decoded position bit stream received from the controller circuit.

2. The system of claim 1, further comprising:

an RFID interrogator configured to interrogate the RFID device and receive in response an RFID identification and a time stamp, wherein the time stamp corresponds to the time maintained by the internal clock.

3. The system of claim 2, further comprising:

a subsystem linked to the RFID interrogator, wherein the subsystem is configured to store the RFID identification and the time stamp.

4. A system comprising:

a radio frequency identification (RFID) device comprising;

an antenna tuned to receive a global positioning system (GPS) speed signal from a public source;

a receiving circuit linked to the antenna, wherein the receiving circuit is configured to convert the received GPS speed signal into a digital speed bit stream;

a controller circuit linked to the receiving circuit, wherein the controller circuit is configured to decode the digital speed bit stream; and

an internal clock linked to the controller circuit, wherein a time maintained by the internal clock is updated based on the decoded speed bit stream received from the controller circuit.

5. The system of claim 4, further comprising:

an RFID interrogator configured to interrogate the RFID device and receive in response an RFID identification and a time stamp, wherein the time stamp corresponds to the time maintained by the internal clock.

6. The system of claim 5, further comprising:

a subsystem linked to the RFID interrogator, wherein the subsystem is configured to store the RFID identification and the time stamp.