Data processing method and device

• US 8,156,284 B2
• Filed: 07/24/2003
• Issued: 04/10/2012
• Est. Priority Date: 08/07/2002
• Status: Active Grant

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Maren Krass, Thomas Richter
• Inventors: Vorbach, Martin, Weinhardt, Markus, Baumgarte, Volker, May, Frank, Becker, Jürgen
• Primary Examiner(s): Thai, Tuan V.
• Application Number:
  US10/523,764
• Publication Number:
  US 20070050603A1
• Time in Patent Office: 3,183 Days
• Field of Search: 711/100, 711/118, 711/154, 711/169, 711/126, 712/1, 712/8, 712/11, 712/15, 712/17
• US Class Current: 711/118
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3455 using stride
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

Claims

1. A data processing arrangement, comprising:

at least one standard processor adapted for processing data in a sequential manner, the at least one standard processor including an instruction pipeline;

a reconfigurable array including a plurality of data processing cells coupled to the at least one standard processor via the instruction pipeline;

a plurality of IRAM memory elements coupled to the reconfigurable array, at least some of the IRAM memory elements forming a data cache for storing local cache copies of a main memory; and

a preloadable configuration cache for storing configuration data, wherein at least some of the data processing cells of the reconfigurable array are coupled to the configuration cache, thereby supporting at least one of preloading of a configuration and a fast configuration switch.

2. The data processing arrangement of claim 1, wherein at least some of the IRAM memory elements include multiple IRAM instances.

3. The data processing arrangement of claim 2, wherein at least some of the IRAM memory elements are associated with a starting address.

4. The data processing arrangement of claim 2, wherein at least some of the IRAM memory elements are associated with a state information.

5. The data processing arrangement of claim 2, wherein at least some of the IRAM memory elements are associated with an address TAG.

6. The data processing arrangement of claim 5, wherein, if no address TAG matches a data access, a corresponding memory area is newly loaded into an empty IRAM instance.

7. The data processing arrangement of claim 6, wherein, if no empty IRAM instance is available, an unmodified instance is declared empty and overwritten with the newly loaded memory area.

8. The data processing arrangement of claim 6, wherein, if no empty IRAM instance is available, a modified instance is cleaned by writing back its data to the main memory.

9. The data processing arrangement of claim 8, wherein a state machine cleans unused IRAM instances by writing back their content in unused memory cycles.

10. The data processing arrangement of claim 2, wherein at least some of the IRAM memory elements are associated with a starting address and with state information.

11. The data processing arrangement of claim 2, wherein at least some of the IRAM memory elements are associated with a starting address and an address TAG.

12. The data processing arrangement of claim 2, wherein at least some of the IRAM memory elements are associated with a starting address, state information, and an address TAG.

13. The data processing arrangement of claim 2, wherein at least some of the IRAM memory elements are associated with state information and an address TAG.

14. The data processing arrangement of any of claims 1, 2, and 3 to 13, wherein the plurality of data processing cells are coarse-grained.

15. The data processing arrangement of claim 14, wherein the reconfigurable array is runtime reconfigurable.

16. The data processing arrangement of claim 15, wherein the reconfigurable array is one of an FPGA, a DSP, and a data-flow-processor.

17. A data processing method, comprising:

providing a reconfigurable array of data processing cells for data processing;

providing at least one standard processor for processing data in a sequential manner, the at least one standard processor including an instruction pipeline via which the reconfigurable array is coupled to the at least one standard processor;

providing a preloadable configuration cache for storing configuration data;

coupling the reconfigurable array to a cache for data processing, the cache containing local cache copies of a main memory, including a plurality of IRAM memory elements, and being explicitly software managed; and

coupling at least some of the data processing cells of the reconfigurable array to the configuration cache, thereby supporting at least one of preloading a configuration and a fast configuration switch.

18. The data processing method of claim 17, wherein the data processing cells are coarse-grained cells.

19. The data processing method of claim 18, wherein the reconfigurable array is runtime reconfigurable.

20. The data processing method of any one of claims 17 to 19, wherein the reconfigurable array is an FPGA.

21. The data processing method of any one of claims 17 to 19, wherein the reconfigurable array is a DSP.

22. The data processing method of any one of claims 17 to 19, wherein the reconfigurable array is a data-flow-processor.

23. The data processing method of claim 17, wherein configurations executed on the reconfigurable array are not pre-emptive.

24. The data processing method of claim 17, wherein the cache containing local cache copies of a main memory eliminates explicit store instructions using cache write-back operations.

25. The data processing method of claim 24, wherein store is executed delayed as cache write back.

26. The data processing method of claim 24, wherein the reconfigurable array supports pipeline stages of Load, Execute, and Store.

27. The data processing method of claim 26, wherein the Store pipeline stage is executed as a cache write-back operation.

28. The data processing method of claim 24, wherein the de-centralized explicitly preloaded configuration cache supports preloading of at least one of a configuration and a fast configuration switch.

29. The data processing system of claim 24, wherein the de-centralized explicitly preloaded configuration cache is implemented as FIFO.

30. The data processing method of claim 24, wherein the reconfigurable array operates asynchronously to the at least one standard processor.

31. The data processing method of claim 24, wherein the reconfigurable array and the at least one standard processor are synchronized via at least one explicit instruction.

32. The data processing method of claim 17, wherein the explicitly software managed cache is preloadable via a configuration configured onto the reconfigurable array.

33. The data processing method of claim 32, wherein the explicitly software managed cache is preloadable via a burst-preload instruction triggered by the at least one standard processor.

34. The data processing method of claim 17, wherein the at least one standard processor is a RISC processor.

35. The data processing method of claim 17, wherein the explicitly software managed cache is written back to the main memory via a synchronization instruction.

36. The data processing method of claim 17, wherein the reconfigurable array supports pipeline stages of Load, Execute, and Store.

37. The data processing method of claim 36, wherein the Store pipeline stage is executed as a cache write-back operation.