Circuits and methods for error coding data blocks

• US 8,161,344 B2
• Filed: 03/11/2008
• Issued: 04/17/2012
• Est. Priority Date: 03/12/2007
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Nygren, Aaron
• Primary Examiner(s): Rizk, Sam
• Application Number:
  US12/046,099
• Publication Number:
  US 20080244358A1
• Time in Patent Office: 1,498 Days
• Field of Search: 714/718, 714/752, 714/758, 714/764, 714/763, 714/773
• US Class Current: 714/752
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

A description is given of a circuit for creating an error coding data block for a first data block, including a first error coding path adapted to create the error coding data block in accordance with a first error coding; and a second error coding path adapted to create the error coding data block in accordance with a second error coding; the error coding data block for the first data block being created optionally by the first or second error coding paths, as a function of a control indicator, and at least the first error coding path comprising a data arrangement alteration device.

Claims

1. A circuit for creating an error coding data block for a first data block, the circuit comprising

a first error coding path adapted to selectively create a first error coding data block in accordance with a first error coding;

and

a second error coding path adapted to selectively create a second error coding data block in accordance with a second error coding;

the first error coding path and the second error coding path being selected as a function of a control indicator, and at least the first error coding path comprising a data arrangement alteration device.

2. The circuit as claimed in claim 1, wherein the first error coding path and the second error coding path are adapted to perform the same data arrangement alteration algorithm for the first and second error codings.

3. The circuit as claimed in claim 2, wherein the first error coding path and the second error coding path comprise a data arrangement alteration device shared by both error coding paths.

4. The circuit as claimed in claim 1, wherein the first error coding path and the second error coding path are adapted to perform the same error coding algorithm for the first and second error codings.

5. The circuit as claimed in claim 4, wherein the first error coding path and the second error coding path comprise an error coding device shared by both error coding paths.

6. The circuit as claimed in claim 1, wherein the first error coding path comprises a first data arrangement alteration device and a first error coder and the second error coding path comprises a second data arrangement alteration device and a second error coder;

the first data arrangement alteration device being adapted to perform a first data arrangement alteration algorithm, and the second data arrangement alteration device being adapted to perform a second data arrangement alteration algorithm which is different from the first data arrangement alteration algorithm; and

the first error coder being adapted to perform a first error coding algorithm, and the second error coder being adapted to perform a second error coding algorithm which is different from the first one.

7. The circuit as claimed in claim 1, wherein the error coding data block for the first data block is selectively created by the first or second error coding paths as a function of the control indicator and a second control indicator.

8. The circuit as claimed in claim 1, wherein the data arrangement alteration device is adapted to create a second data block, comprising a given number of data in a second arrangement, on the basis of the first data block comprising the given number of data in a first arrangement, in accordance with a data arrangement alteration algorithm.

9. The circuit as claimed in claim 1, wherein an input of the circuit is a parallel input which may receive several data at the same time.

10. The circuit as claimed in claim 1, wherein an error coding device is adapted to perform an error detection or error correction algorithm as an error coding algorithm.

11. The circuit as claimed in claim 1, wherein an error coding device is adapted to perform a cyclic redundancy code algorithm as an error coding algorithm.

12. The circuit as claimed in claim 1, wherein the control indicator is dependent on an operating mode.

13. The circuit as claimed in claim 1, which is an integrated circuit.

14. The circuit as claimed in claim 1, wherein the circuit is a graphic memory device.

15. The circuit as claimed in claim 1, wherein the circuit is a graphic dynamic random access memory device.

16. A system comprising

a processor;

a memory; and

a circuit coupled between the processor and the memory, the circuit for creating an error coding data block for a first data block, the circuit comprising;

a first error coding path adapted to selectively create a first error coding data block in accordance with a first error coding; and

a second error coding path adapted to selectively create a second error coding data block in accordance with a second error coding;

the first error coding path and the second data path being selected as a function of a control indicator, and at least the first error coding path comprising a data arrangement alteration device.

17. The system as claimed in claim 16, wherein the memory is selected to store information of the first data block along with the error coding data block in a writing operation.

18. The system as claimed in claim 16, wherein the circuit is adapted to read out the information of the first data block along with the error coding data block in a reading operation;

and

to perform, by means of the error coding data block, an error detection or error correction for read-out information of the first data block.

19. An apparatus for creating an error coding data block for a first data block, the apparatus comprising:

first means for selectively performing a first error coding so as to create a first error coding data block; and

second means for selectively performing a second error coding so as to create a second error coding data block;

the first means and the second means being selected as a function of a control indicator, and at least the first means for performing the first error coding comprising a means for performing a data arrangement alteration algorithm.

20. The apparatus as claimed in claim 19, wherein the first means for performing the first error coding and the second means for performing the second error coding are adapted to perform the same data arrangement alteration algorithm for the first and second error codings.

21. The apparatus as claimed in claim 20, wherein the first means for performing the first error coding and the second means for performing the second error coding comprise a means, shared by the two means for performing the data arrangement alteration algorithm.

22. The apparatus as claimed in claim 19, wherein the first means for performing the first error coding and the second means for performing the second error coding are adapted to perform the same error coding algorithm for the first and second error codings.

23. The apparatus as claimed in claim 22, wherein the first means for performing the first error coding and the second means for performing the second error coding comprise a means, shared by the two means for performing an error coding algorithm.

24. The apparatus as claimed in claim 19, wherein the first means for performing the first error coding comprises a first means for performing a first data arrangement alteration algorithm and a first means for performing a first error coding algorithm;

and the second means for performing the second error coding comprises a second means for performing a second data arrangement alteration algorithm and a second means for performing as second error coding algorithm;

the first data arrangement alteration algorithm being different from the second data arrangement alteration algorithm; and

the first error coding algorithm being different from the second error coding algorithm.

25. The apparatus as claimed in claim 19, wherein the error coding data block is selectively created by the first means for performing the first error coding or by the second means for performing the second error coding as a function of the control indicator and a second control indicator.

26. The apparatus as claimed in claim 19, wherein a means for performing a data arrangement alteration algorithm is adapted to create a second data block, comprising a given number of data in a second arrangement, on the basis of the first data block comprising the given number of data in a first arrangement, in accordance with the data arrangement alteration algorithm.

27. The apparatus as claimed in claim 19 which is adapted to receive several data at the same time.

28. The apparatus as claimed in claim 19, wherein a means for performing an error coding algorithm is adapted to perform an error detection or error correction algorithm as the error coding algorithm.

29. The apparatus as claimed in claim 19, wherein a means for performing an error coding algorithm is adapted to perform a cyclic redundancy code algorithm as the error coding algorithm.

30. The apparatus as claimed in claim 19, wherein the control indicator is dependent on an operating mode.

31. The apparatus as claimed in claim 19, wherein the apparatus is a graphic memory device.

32. The apparatus as claimed in claim 19, wherein the apparatus is a graphic dynamic random access memory device.

33. A circuit for creating an error coding data block for a first data block, the circuit comprising:

a data arrangement alteration device comprising an input and an output, the data arrangement alteration device being adapted to receive, at the input, a first data block comprising a given number of data in a first arrangement, and to create, on the basis of the first data block, a second data block comprising a given number of data in a second arrangement, and to output same at the output; and

an error coder comprising an input and an output, the input being coupled to a first control output of a controller, the input of the error coder being coupled to the output of the data arrangement alteration device, the error coder being adapted to create, on the basis of the second data block, a coding data block and to output same at the output of the error coder,

the data arrangement alteration device further comprising a control input and being adapted to create the second data block as a function of a first control indicator in accordance with a first or second data arrangement alteration algorithm,

and/or

the error coder further comprising a control input and being adapted to create the error coding data block as a function of the first control indicator in accordance with a first or second error coding algorithm.

34. The circuit as claimed in claim 33, wherein the data arrangement alteration device is adapted to create the second data block in accordance with the first data arrangement alteration algorithm, and the error coder is adapted to create the error coding data block in accordance with the first error coding algorithm, if the first control indicator comprises a first value, and

wherein the data arrangement alteration device is adapted to create the second data block in accordance with the second data arrangement alteration algorithm, and the error coder is adapted to create the error coding data block in accordance with the second error coding algorithm, if the first control indicator comprises a second value which differs from the first value.

35. The circuit as claimed in claim 33, wherein the error coder is adapted to create the error coding data block as a function of a second control indicator in accordance with the first or second error coding algorithm.

36. The circuit as claimed in claim 33, wherein the input of the data arrangement alteration device is a parallel input which may receive several data at the same time.

37. The circuit as claimed in claim 33, wherein the error coding algorithms are error detection or error correction algorithms.

38. The circuit as claimed in claim 33, wherein the error coding algorithm is a cyclic redundancy code algorithm.

39. The circuit as claimed in claim 33, wherein the data arrangement alteration device comprises a deserializer, a programmable logic component and a multiplexer, the deserializer being adapted to convert a first data block to a parallel intermediate arrangement, so that all data of the first data block are arranged in parallel with one another.

40. The circuit as claimed in claim 33, wherein the circuit is a memory interface device.

41. The circuit as claimed in claim 40, wherein the input of the data arrangement alteration device is a parallel input which may receive several data at the same time, and the data arrangement alteration device is adapted to receive, in a burst mode, the first data block over several clock pulses.

42. The circuit as claimed in claim 33, wherein the first control indicator is provided by a control device, for example by a mode register.

43. A method of creating an error coding data block for a first data block, the method comprising:

receiving the first data block;

selectively performing a first error coding via a first path so as to create a first error coding data block;

selectively performing a second error coding via a second path so as to create a second error coding data block;

the first error coding data block for the first data block and the second error coding data block being selectively created as a function of a control indicator, wherein at least the step of selectively performing the first error coding comprises the step of performing a data arrangement alteration algorithm.

44. The method as claimed in claim 43, wherein performing the first error coding and performing the second error coding comprise performing the same data arrangement alteration algorithm.

45. The method as claimed in claim 43, wherein performing the first error coding and the second error coding comprise performing the same error coding algorithm.

46. The method as claimed in claim 43, wherein performing the first error coding comprises performing a first data arrangement alteration algorithm and performing a first error coding algorithm;

and performing a second error coding comprises performing a second data arrangement alteration algorithm and performing a second error coding algorithm;

the first data arrangement alteration algorithm being different from the second data arrangement alteration algorithm; and

the first error coding algorithm being different from the second error coding algorithm.

47. The method as claimed in claim 43, wherein the error coding data block for the first data block is selectively created by performing the first error coding or by performing the second error coding, as a function of a control indicator and a second control indicator.

48. The method as claimed in claim 43, wherein receiving the first data block comprises receiving several data at the same time.

49. The method as claimed in claim 43, wherein the error coding algorithm is an error detection or an error correction algorithm.

50. The method as claimed in claim 43, wherein the error coding algorithm is a cyclic redundancy code algorithm.

51. The method as claimed in claim 43, wherein the value of the control indicator depends on an operating mode.