Digitally controlled phase interpolator circuit
First Claim
1. An apparatus, comprising:
- a plurality of differential pairs of transistors such that gates of each differential pair of transistors for receiving a respective differential input clock signal, sources of each differential pair of transistors connected, and drains of each differential pair of transistors for outputting a differential output clock signal;
a plurality of switches for selectively enabling a plurality of current supplies to supply current respectively to connected sources of at least one selected transistor of the plurality of differential transistors based on a plurality of control words such that each of the plurality of switch control words corresponding to one of the plurality of switches, wherein each of the plurality of switch control words being respectively generated from 2 quadrant indicating bits and one respective phase interpolating bit; and
at least one additional current supply for continuously supplying at least one additional current to connected sources of at least one of the plurality of differential transistors.
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Accused Products
Abstract
Digitally controlled phase interpolator circuit. A phase selection control word undergoes decoding to generate a switch control word. The phase selection control word includes 2 quadrant indicating bits and phase interpolating bits for a 4 clock scheme (e.g., 4 clocks having phases 0°, 90°, 180°, and 270°). Such a phase selection control word could includes 3 sector indicating bits and phase interpolating bits for an 8 clock scheme (e.g., 8 clocks having phases 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). The gates of a number of differential pairs of transistors receive the various clock signals. A number of switching circuits direct current from corresponding current sources/supplies to coupled sources of the differential pairs of transistors, and an output clock is taken from coupled drains of the differential pairs of transistors. One or more current sources/supplies can be implemented to provide continuous current (e.g., in an always on manner) to the differential pairs of transistors.
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Citations
20 Claims
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1. An apparatus, comprising:
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a plurality of differential pairs of transistors such that gates of each differential pair of transistors for receiving a respective differential input clock signal, sources of each differential pair of transistors connected, and drains of each differential pair of transistors for outputting a differential output clock signal; a plurality of switches for selectively enabling a plurality of current supplies to supply current respectively to connected sources of at least one selected transistor of the plurality of differential transistors based on a plurality of control words such that each of the plurality of switch control words corresponding to one of the plurality of switches, wherein each of the plurality of switch control words being respectively generated from 2 quadrant indicating bits and one respective phase interpolating bit; and at least one additional current supply for continuously supplying at least one additional current to connected sources of at least one of the plurality of differential transistors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus, comprising:
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a plurality of differential pairs of transistors such that gates of each differential pair of transistors for receiving a respective differential input clock signal, sources of each differential pair of transistors connected, and drains of each differential pair of transistors for outputting a differential output clock signal; a first plurality of switches for selectively enabling a first current supply to supply first current respectively to connected sources of a first at least one selected transistor of the plurality of differential transistors based on a first switch control word based on 2 quadrant indicating bits and a first phase interpolating bit; a second plurality of switches for selectively enabling a second current supply to supply second current respectively to connected sources of a second at least one selected transistor of the plurality of differential transistors based on a second switch control word based on the 2 quadrant indicating bits and a second phase interpolating bit; and a third current supply for continuously supplying third current to connected sources of at least one of the plurality of differential transistors. - View Dependent Claims (12, 13, 14, 15, 16)
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17. An apparatus, comprising:
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a plurality of decoders for; processing 2 quadrant indicating bits and a first phase interpolating bit thereby generating a first switch control word; and processing the 2 quadrant indicating bits and a second phase interpolating bit thereby generating a second switch control word having a same number of bits as the first switch control word; a plurality of differential pairs of transistors such that gates of each differential pair of transistors for receiving a respective differential input clock signal, sources of each differential pair of transistors connected, and drains of each differential pair of transistors for outputting a differential output clock signal; a first plurality of switches for selectively enabling a first current supply to supply first current respectively to connected sources of a first at least one selected transistor of the plurality of differential transistors based on the first switch control word; a second plurality of switches for selectively enabling a second current supply to supply second current respectively to connected sources of a second at least one selected transistor of the plurality of differential transistors based on the second switch control word; and a third current supply for continuously supplying third current to connected sources of at least one of the plurality of differential transistors. - View Dependent Claims (18, 19, 20)
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Specification