D-cache line use history based done bit based on successful prefetchable counter

• US 8,171,224 B2
• Filed: 05/28/2009
• Issued: 05/01/2012
• Est. Priority Date: 05/28/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Luick, David A.
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Norman, James G
• Application Number:
  US12/473,328
• Publication Number:
  US 20100306471A1
• Time in Patent Office: 1,069 Days
• Field of Search: None
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/127 using additional replacement algorithms

Abstract

A method of providing history based done logic for a D-cache includes receiving a D-cache line in an L2 cache; determining if the D-cache line is unprefetchable; aging the D-cache line without a delay if the D-cache line is prefetchable; and aging the D-cache line with a delay if the D-cache line is unprefetchable.

Claims

1. A method of providing history based done logic for a D-cache, the method comprising:

receiving a D-cache line in an L2 cache;

determining if the D-cache line is unprefetchable;

aging the D-cache line without a delay if the D-cache line is prefetchable; and

aging the D-cache line with a delay if the D-cache line is unprefetchable;

wherein the D-cache line includes a demand stall flag, an aging flag, a history count and a reference count.

2. The method of claim 1, wherein the determining further comprises updating the reference count in an L1 D-cache and the L2 D-cache each time the D-cache line is accessed.

3. The method of claim 1, further comprising aging the D-cache line at a rate indicated by the aging flag if a demand stall flag indicates that D-cache line is unprefetchable.

4. An integrated circuit device comprising:

a processor core;

a level one (L1) cache;

a level two (L2) cache;

an aging count in the L1 cache for indicating a number of least recently used demotions to be skipped between actual demotions to a D-cache line in the L1 cache, wherein the D-cache line includes a demand stall flag and an aging flag;

a counter that counts each time the D-cache line is referenced in the L1 cache; and

a comparator for comparing a history count to a reference count to determine when the reference count is equal to the history count for a D-cache line.

5. The integrated circuit device of claim 4, wherein the counter updates a reference counter in the L2 cache each time the D-cache line is referenced in the L1 cache.

6. The integrated circuit device of claim 4, wherein the D-cache line is aged at a rate indicated by the aging flag if a demand stall flag indicates that D-cache line is unprefetchable.

7. A processor device, comprising:

a level one (L1) cache;

a level two (L2) cache;

circuitry configured to receive a D-cache line in the L2 cache, determine if the D-cache line is unprefetchable, age the D-cache line without a delay if the D-cache line is prefetchable; and

age the D-cache line with a delay if the D-cache line is unprefetchable;

wherein the D-cache line includes a demand stall flag, an aging flag, a history count and a reference count.

8. The processor device of claim 7, wherein determining further comprises updating the reference count in the L1 D-cache and the L2 D-cache each time the D-cache line is accessed.

9. The processor device of claim 7, further comprising aging the D-cache line at a rate indicated by the aging flag if a demand stall flag indicates that D-cache line is unprefetchable.