Power-aware debugging
First Claim
1. A computer-readable storage device containing software which, when executed by a computer, causes the computer to carry out a method of processing an integrated circuit (IC) design and results of a logic simulation of a behavior of a simulated version of an IC based on the IC design, wherein the IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising a plurality of cell instances communicating via data signals and power sources for supplying power to the cell instances, and a power definition markup language (PDML) model describing a power intent of the IC design, the method comprising steps of:
- a. responding to a user input by generating a display representing a portion of the HDL model of the IC, andb. augmenting the display to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display.
3 Assignments
0 Petitions
Accused Products
Abstract
A debugging system produces displays in response to an IC design and results of a logic simulation of IC behavior based on the IC design. The IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising cell instances communicating via data signals and power sources for supplying power to the cell instances. The IC design also includes power definition markup language (PDML) model describing a power intent of the IC design. The debugging system generates displays representing HDL code that are annotated to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. The debugging system also generates signals trace displays indicating how both the logic and power intent of the IC design affect the value of a user-selected signal at a user-selected time during the logic simulation.
21 Citations
19 Claims
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1. A computer-readable storage device containing software which, when executed by a computer, causes the computer to carry out a method of processing an integrated circuit (IC) design and results of a logic simulation of a behavior of a simulated version of an IC based on the IC design, wherein the IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising a plurality of cell instances communicating via data signals and power sources for supplying power to the cell instances, and a power definition markup language (PDML) model describing a power intent of the IC design, the method comprising steps of:
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a. responding to a user input by generating a display representing a portion of the HDL model of the IC, and b. augmenting the display to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification