Semiconductor device

• US 8,178,947 B2
• Filed: 10/01/2008
• Issued: 05/15/2012
• Est. Priority Date: 05/13/2008
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Takahashi, Tetsuo, Tomomatsu, Yoshifumi
• Primary Examiner(s): Mandala, Victor A
• Assistant Examiner(s): HARRISTON, WILLIAM A
• Application Number:
  US12/243,335
• Publication Number:
  US 20090283797A1
• Time in Patent Office: 1,322 Days
• Field of Search: 257/565, 257/139, 257/329, 257/330, 257/331, 257/579, 257/E29.171, 257/E29.198, 257/E21.027, 257/E29.04, 257/E29.201, 257/E21.384, 257/E21.383
• US Class Current: 257/565
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

There is provided a semiconductor device in which an amount of fluctuations in output capacitance and feedback capacitance is reduced. In a trench-type insulated gate semiconductor device, a width of a portion of an electric charge storage layer in a direction along which a gate electrode and a dummy gate are aligned is set to be at most 1.4 μm.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having first and second main surfaces;

a first impurity region of a first conductivity type between said first main surface and said second main surface;

a second impurity region of a second conductivity type at said second main surface;

a first groove portion at said first main surface and reaching said first impurity region;

a first electrode in said first groove portion with a first insulating film interposed therebetween;

a second groove portion apart from said first groove portion and reaching said first impurity region from said first main surface;

a second electrode in said second groove portion with a second insulating film interposed therebetween;

a gate wiring connected to said first electrode and capable of applying a gate voltage to the first electrode;

a third impurity region of said first conductivity typed at a position of said first main surface adjacent to said first electrode on a side facing said second electrode;

a fourth impurity region of the second conductivity type at said first main surface between said first electrode and said second electrode and surrounding said third impurity region;

a main electrode on said first main surface and connected to said third impurity region and said fourth impurity region;

an interlayer insulating film on said first electrode and capable of insulating said main electrode and said first electrode from each other;

a fifth impurity region of the first conductivity type between said first and second electrodes and between said fourth impurity region and said first impurity region and having an impurity concentration higher than an impurity concentration of said first impurity region; and

a sixth impurity region of said second conductivity type at said first main surface adjacent to said second electrode on a side opposite to said fourth impurity region with respect to said second electrode, wherein

said main electrode extends in the direction along which said first and second electrodes are aligned, and is connected to said second electrode, and

said interlayer insulating film is on said sixth impurity region to insulate said sixth impurity region and said main electrode from each other.

2. The semiconductor device according to claim 1, further comprising a third groove portion in said sixth impurity region and splitting said sixth impurity region, and a third electrode in said third groove portion with a third insulating film interposed therebetween, wherein said third electrode is connected to said main electrode.

3. The semiconductor device according to claim 2, wherein a depth of said third electrode is larger than a depth of said second electrode.

4. The semiconductor device according to claim 2, wherein a width of said third electrode is larger than a width of said second electrode.

12. The semiconductor device according to claim 1, wherein a width of said fifth impurity region in a direction along which said first electrode and said second electrode are aligned is at most 1.4 μ

m.

13. The semiconductor device according to claim 12, wherein said width of said fifth impurity region is at most 1.2 μ

m.

5. A semiconductor device, comprising:

a semiconductor substrate having first and second main surfaces;

a first impurity region of a first conductivity type between said first main surface and said second main surface;

a second impurity region of a second conductivity type at said second main surface;

a first groove portion at said first main surface and reaching said first impurity region;

a first electrode in said first groove portion with a first insulating film interposed therebetween;

a second groove portion apart from said first groove portion and reaching said first impurity region from said first main surface;

a second electrode in said second groove portion with a second insulating film interposed therebetween;

a gate wiring connected to said first electrode and capable of applying a gate voltage to the first electrode;

a third impurity region of said first conductivity typed at a position of said first main surface adjacent to said first electrode on a side facing said second electrode;

a fourth impurity region of the second conductivity type at said first main surface located between said first electrode and said second electrode and surrounding said third impurity region;

a main electrode on said first main surface and connected to said third impurity region and said fourth impurity region;

an interlayer insulating film on said first electrode and capable of insulating said main electrode and said first electrode from each other;

a fifth impurity region of the first conductivity type between said first and second electrodes and between said fourth impurity region and said first impurity region, and having an impurity concentration higher than an impurity concentration of said first impurity region and a width in a direction along which said first electrode and said second electrode are aligned of at most 1.4 μ

m;

a third groove portion apart from said second groove portion;

a third electrode in said third groove portion with a third insulating film interposed therebetween;

a fourth groove portion provided apart from said third groove portion on a side opposite to said second groove portion with respect to said third groove portion; and

a fourth electrode in said fourth groove portion with a fourth insulating film interposed therebetween, wherein

said second electrode is connected to said gate wiring, and

said fourth electrode is connected to said gate wiring, and said third electrode is connected to said main electrode.

6. The semiconductor device according to claim 5, wherein the width of said fifth impurity region is at most 1.2 μ

m.

7. The semiconductor device according to claim 5, further comprising a sixth impurity region on a main surface of said semiconductor substrate between said second electrode and the third electrode, and on the main surface of said semiconductor substrate between said third electrode and the fourth electrode, and electrically separated from said main electrode by said interlayer insulating film.

8. The semiconductor device according to claim 7, wherein

a plurality of said third electrodes are apart from one another, on the main surface of said semiconductor substrate located between said second electrode and said fourth electrode, and said sixth impurity region is on the main surface of said semiconductor substrate located between said third electrodes.

9. The semiconductor device according to claim 8, wherein a spacing between said third electrode and said second electrode is smaller than a spacing between said third electrodes.

10. The semiconductor device according to claim 5, wherein a width of said third electrode is larger than a width of each of said first and second electrodes.

11. The semiconductor device according to claim 5, wherein a depth of said third electrode is larger than a depth of each of said first and second electrodes.

14. A semiconductor device, comprising:

a semiconductor substrate having first and second main surfaces;

a first impurity region of a first conductivity type between said first main surface and said second main surface;

a second impurity region of a second conductivity type at said second main surface;

a first groove portion at said first main surface and reaching said first impurity region;

a first electrode in said first groove portion with a first insulating film interposed therebetween;

a second groove portion in said first main surface, apart from and on a first side of said first groove portion, and reaching said first impurity region;

a second electrode in said second groove portion with a second insulating film interposed therebetween;

a third groove portion in said first main surface, apart from and on a second side of said first groove portion opposite to said first side, and reaching said first impurity region;

a third electrode in said third groove portion with a third insulating film interposed therebetween;

a gate wiring connected to said first electrode and capable of applying a gate voltage to the first electrode;

a third impurity region of said first conductivity type at said first main surface and positioned adjacent to said first electrode;

a fourth impurity region of the second conductivity type at said first main surface between said first electrode and said second electrode and surrounding said third impurity region;

a main electrode on said first main surface and electrically connected to said third impurity region and said second electrode;

an interlayer insulating film on said first electrode and insulating said main electrode and said first electrode from each other; and

a fifth impurity region of the first conductivity type having impurity concentration higher than impurity concentration of said first impurity region, positioned between said first and second electrodes and between said fourth impurity region and said first impurity region, and having a width in a direction along which said first electrode and said second electrode are aligned of at most 1.4 μ

m.

15. The semiconductor device according to claim 14, wherein said width of said fifth impurity region is at most 1.2 μ

m.

16. The semiconductor device according to claim 14, further comprising:

a sixth impurity region of said first conductivity type at said first main surface and positioned adjacent to said first electrode on a side of said first electrode opposite to said third impurity region; and

a seventh impurity region of the second conductivity type at said first main surface between said first electrode and said third electrode and surrounding said sixth impurity region,

wherein said main electrode electrically connects said sixth impurity region and said third electrode.

17. The semiconductor device according to claim 16, further comprising a eighth impurity region of the first conductivity type having an impurity concentration higher than an impurity concentration of said first impurity region, said eighth impurity region positioned between said first and third electrodes and between said seventh impurity region and said first impurity region, and having a width in a direction along which said first electrode and said third electrode are aligned of at most 1.4 μ

m.

18. The semiconductor device according to claim 14, further comprising an electrically floating impurity region of said second conductivity type at said first main surface and adjacent to said second electrode on a side opposite to said fourth impurity region with respect to said second electrode.

19. The semiconductor device according to claim 18, further comprising:

a fourth groove portion in said first main surface and splitting said electrically floating impurity region; and

a fourth electrode in said fourth groove portion with a fourth insulating film interposed therebetween, wherein

said main electrode is electrically connected to said fourth electrode.

20. The semiconductor device according to claim 19, wherein depth of said fourth electrode is larger than a depth of each of said first and second electrodes.

21. The semiconductor device according to claim 19, wherein a spacing between said fourth electrode and said second electrode is smaller than a spacing between said first and second electrodes.

22. The semiconductor device according to claim 19, wherein a width of said fourth electrode is larger than a width of said second electrode.

23. A semiconductor device, comprising:

a semiconductor substrate having first and second main surfaces;

a first impurity region of a first conductivity type between said first main surface and said second main surface;

a second impurity region of a second conductivity type at said second main surface;

a first groove portion at said first main surface and reaching said first impurity region;

a first electrode in said first groove portion with a first insulating film interposed therebetween;

a second groove portion apart from said first groove portion and reaching said first impurity region from said first main surface;

a second electrode in said second groove portion with a second insulating film interposed therebetween;

a gate wiring connected to said first electrode and capable of applying a gate voltage to the first electrode;

a third impurity region of said first conductivity type at a position of said first main surface adjacent to said first electrode on a side facing said second electrode;

a fourth impurity region of the second conductivity type at said first main surface located between said first electrode and said second electrode and said third impurity region;

a main electrode on said first main surface and connected to said third impurity region and said fourth impurity region;

an interlayer insulating film on said first electrode and capable of insulating said main electrode and said first electrode from each other;

a fifth impurity region of the first conductivity type between said first and second electrodes and between said fourth impurity region and said first impurity region, and having an impurity concentration higher than an impurity concentration of said first impurity region and a width in a direction along which said first electrode and said second electrode are aligned of at most 1.4 μ

m;

a third groove portion apart from said second groove portion;

a third electrode in said third groove portion with a third insulating film interposed therebetween;

a fourth groove portion provided apart from said third groove portion on a side opposite to said second groove portion with respect to said third groove portion; and

a fourth electrode in said fourth groove portion with a fourth insulating film interposed therebetween, wherein

said second electrode is connected to said gate wiring, and

said fourth electrode and said third electrode are connected to said main electrode.

24. The semiconductor device according to claim 23, further comprising a sixth impurity region on a main surface of said semiconductor substrate between said second electrode and the third electrode, and on the main surface of said semiconductor substrate between said third electrode and the fourth electrode, and electrically separated from said main electrode by said interlayer insulating film.

25. The semiconductor device according to claim 24, wherein

a plurality of said third electrodes are apart from one another, on the main surface of said semiconductor substrate located between said second electrode and said fourth electrode, and said sixth impurity region is on the main surface of said semiconductor substrate located between said third electrodes.

26. The semiconductor device according to claim 25, wherein a spacing between said third electrode and said second electrode is smaller than a spacing between said third electrodes.

27. The semiconductor device according to claim 23, wherein a width of said third electrode is larger than a width of each of said first and second electrodes.

28. The semiconductor device according to claim 23, wherein a depth of said third electrode is larger than a depth of each of said first and second electrodes.

29. The semiconductor device according to claim 23, wherein the width of said fifth impurity region is at most 1.2 μ

m.