Maintaining integrity of preloaded content in non-volatile memory during surface mounting

• US 8,179,717 B2
• Filed: 09/29/2009
• Issued: 05/15/2012
• Est. Priority Date: 09/29/2009
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Shepard, Zac, Yang, Xiaoyu, Meeks, Albert, Li, Qing, Levi, Enosh, Le, Kim, Dan, Raz, Murphy, Brian
• Primary Examiner(s): Nguyen, Tuan T
• Assistant Examiner(s): REIDLINGER, RONALD LANCE
• Application Number:
  US12/569,869
• Publication Number:
  US 20110075482A1
• Time in Patent Office: 959 Days
• Field of Search: 438/106, 36518501-18533, 365/201
• US Class Current: 365/185.02
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A non-volatile memory chip package is prepared for surface mounting to a substrate in a solder reflow process by programming erased blocks to higher threshold voltage levels, to improve data retention for blocks which are preloaded with content, such as by an electronic device manufacturer. Following the surface mounting, the previously-erased blocks are returned to the erased state. The threshold voltage of storage elements of the preloaded blocks can change during the surface mounting process due to a global charge effect phenomenon. The effect is most prominent for higher state storage elements which are surrounded by erased blocks, in a chip for which the wafer backside was thinned and polished. The erased blocks can be programmed using a single program pulse without performing a verify operation, as a wide threshold voltage distribution is acceptable.

Claims

1. A method for preparing a non-volatile memory chip package, including preparing the non-volatile memory chip package for surface mounting to a substrate in a surface mounting process which heats the non-volatile memory chip package, the non-volatile memory chip package comprises a die comprising a plurality of blocks of non-volatile storage elements, the method comprising:

preloading a block of the plurality of blocks with data;

identifying a block of the plurality of blocks which is not preloaded with data, the block which is not preloaded with data is in an erased state;

responsive to the identifying, raising threshold voltages of non-volatile storage elements of the block which is not preloaded with data, from an initial level which is a level of the erased state, to higher levels; and

following the surface mounting process, erasing the non-volatile storage elements of the block which is not preloaded with data to the erase state.

2. The method of claim 1, further comprising:

placing the non-volatile memory chip package on the substrate after the preloading and the raising.

3. The method of claim 1, wherein:

the block which is preloaded with data uses at least four data states to store the data, the at least four data states includes a highest data state which has an associated verify level, and a second highest data state which has an associated verify level; and

the higher levels are at least as high as the associated verify level of the second highest data state, for a non-volatile storage element in the block which is not preloaded with data.

4. The method of claim 1, wherein:

the block which is preloaded with data uses at least eight data states to store the data, the at least eight data states include a highest data state which has an associated verify level, a second highest data state which has an associated verify level, and a third highest data state which has an associated verify level; and

the higher levels are at least as high as the associated verify level of the third highest data state, for a non-volatile storage element in the block which is not preloaded with data.

5. The method of claim 1, wherein:

the substrate is a printed circuit board; and

the surface mounting process comprises a solder reflow process in which the non-volatile memory chip package is soldered to the printed circuit board.

6. The method of claim 1, wherein:

the plurality of blocks of non-volatile storage elements are on a common die.

7. A method for preparing a non-volatile memory chip package, including preparing the non-volatile memory chip package for surface mounting to a substrate in a surface mounting process which heats the non-volatile memory chip package, the non-volatile memory chip package comprises a die comprising a plurality of blocks of non-volatile storage elements, the method comprising:

preloading a block of the plurality of blocks with data;

identifying a block of the plurality of blocks which is not preloaded with data;

responsive to the identifying, raising threshold voltages of non-volatile storage elements of the block which is not preloaded with data, from an initial level to higher levels, the raising the threshold voltages comprises applying a program pulse to the non-volatile storage elements of the block which is not preloaded with data, without performing a verifying operation.

8. A non-transitory processor readable storage device having processor readable code embodied thereon for programming one or more processors to perform a computer implemented method for preparing a non-volatile memory chip package, including preparing the non-volatile memory chip package for surface mounting to a substrate in a surface mounting process which heats the non-volatile memory chip package, the non-volatile memory chip package comprises a die comprising a plurality of blocks of non-volatile storage elements, the method comprising:

preloading a block of the plurality of blocks with data;

identifying a block of the plurality of blocks which is not preloaded with data; and

responsive to the identifying, raising threshold voltages of non-volatile storage elements of the block which is not preloaded with data from an initial level to higher levels, the block which is preloaded with data uses at least four data states to store the data, the at least four data states includes a highest data state which has an associated verify level, and a second highest data state which has an associated verify level, and the higher levels are at least as high as the associated verify level of the second highest data state, for a non-volatile storage element in the block which is not preloaded with data.

9. The non-transitory processor readable storage device of claim 8, wherein the block which is not preloaded with data is in an erased state, and the initial level is a level of the erased state, the method further comprising:

following the surface mounting process, erasing the non-volatile storage elements of the block which is not preloaded with data to the erase state.

10. The non-transitory processor readable storage device of claim 8, wherein:

the block which is preloaded with data uses at least eight data states to store the data, the at least eight data states include a highest data state which has an associated verify level, a second highest data state which has an associated verify level, and a third highest data state which has an associated verify level; and

the higher levels are at least as high as the associated verify level of the third highest data state, for a non-volatile storage element in the block which is not preloaded with data.

11. The non-transitory processor readable storage device of claim 8, wherein:

the raising the threshold voltages comprises applying a program pulse to the non-volatile storage elements of the block which is not preloaded with data, without performing a verifying operation.

12. The non-transitory processor readable storage device of claim 8, wherein:

the non-volatile storage elements whose threshold voltages are raised are provided in a quincunx pattern with other non-volatile storage elements in the block which are not preloaded with data, and whose threshold voltages are not raised.

13. A non-transitory processor readable storage device having processor readable code embodied thereon for programming one or more processors to perform a computer implemented method for preparing a non-volatile memory chip package, including preparing the non-volatile memory chip package for surface mounting to a substrate in a surface mounting process which heats the non-volatile memory chip package, the non-volatile memory chip package comprises a die comprising a plurality of blocks of non-volatile storage elements, the method comprising:

preloading a block of the plurality of blocks with data;

identifying a block of the plurality of blocks which is not preloaded with data; and

responsive to the identifying, raising threshold voltages of non-volatile storage elements of the block which is not preloaded with data from an initial level to higher levels, the non-volatile storage elements whose threshold voltages are raised are provided in a quincunx pattern with other non-volatile storage elements in the block which are not preloaded with data, and whose threshold voltages are not raised.

14. A method for preparing a non-volatile memory chip package, including preparing the non-volatile memory chip package for surface mounting to a substrate in a surface mounting process which heats the non-volatile memory chip package, the non-volatile memory chip package comprises a plurality of die, each die comprises a plurality of blocks of non-volatile storage elements, the method comprising:

programming a block of a die of the plurality of die with data;

identifying a block of the die which is not programmed with data, and which is in an erased state;

identifying another die of the plurality of die which is not programmed with data, and which has blocks in the erased state; and

raising threshold voltages of non-volatile storage elements of the block which is not programmed with data above the erased state, where the blocks in the erased state of the another die which is not programmed with data are kept in the erased state.

15. The method of claim 14, further comprising:

following the surface mounting process, erasing the non-volatile storage elements of the block which is not programmed with data, and which has non-volatile storage elements with their threshold voltages raised above the erased state.

16. The method of claim 14, wherein:

the block which is programmed with data uses at least four data states to store the data, the at least four data states include a highest data state which has an associated verify level, and a second highest data state which has an associated verify level; and

the non-volatile storage elements which have their threshold voltages raised above the erased state include a non-volatile storage element which has its threshold voltage raised above the associated verify level of the second highest data state.

17. The method of claim 14, wherein:

the raising the threshold voltages comprises applying a program pulse to the non-volatile storage elements of the block which is not programmed with data, without performing a verifying operation.

18. The method of claim 14, wherein:

the substrate is a printed circuit board; and

the surface mounting process comprises a solder reflow process in which the non-volatile memory chip package is soldered to the printed circuit board.