Semiconductor integrated circuit and control method for clock signal synchronization

• US 8,183,899 B2
• Filed: 11/10/2009
• Issued: 05/22/2012
• Est. Priority Date: 11/11/2008
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kanno, Yusuke, Saen, Makoto, Komatsu, Shigenobu, Onouchi, Masafumi
• Primary Examiner(s): O NEILL, PATRICK
• Application Number:
  US12/615,607
• Publication Number:
  US 20100117697A1
• Time in Patent Office: 924 Days
• Field of Search: 327/149, 327/153, 327/158, 327161-163
• US Class Current: 327/149
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.

Claims

1. A semiconductor integrated circuit comprising:

a first circuit that operates using a first power-supply voltage supplied from a power supplying Large Scale Integration (LSI) circuit;

a second circuit that operates using a second power-supply voltage;

a clock generation circuit that generates a clock;

a clock tree that transmits the clock generated by the clock generation circuit to the first circuit and the second circuit;

a clock synchronization circuit having a plurality of delay stages that perform clock delay adjustment between a first path for transmitting the clock to the first circuit and a second path for transmitting the clock to the second circuit along the clock tree to synchronize the clock in the first and second paths; and

a control circuit that notifies the power supplying LSI circuit of change control over the first power-supply voltage,

wherein the power supplying LSI circuit is notified of a voltage change velocity for applying variable control to the first power-supply voltage,

wherein control is performed to match a phase between the clock as supplied to the first circuit and the clock as supplied to the second circuit when a voltage of the first circuit is changed at the voltage change velocity, and

wherein the clock synchronization circuit comprises;

a second comparison circuit for comparing a phase between a clock output signal from a variable delay circuit and a clock signal propagated along a through path thereof; and

a delay control circuit for controlling a delay setting provided by the variable delay circuit,

wherein the delay control circuit, based on a comparison result from the second comparison circuit, sets a delay equivalent to an integral multiple of a clock cycle to an output from the variable delay circuit in accordance with the clock signal propagated along the through path,

wherein the delay control circuit responds to an instruction to change the first power-supply voltage from a standard voltage to another voltage,

wherein the delay control circuit allows a selection circuit to select an output from the variable delay circuit and adjusts a delay setting of the variable delay circuit based on a comparison result from a first comparison circuit, and

wherein the delay control circuit controls phase synchronization between the clock transmitted to the first circuit and the clock transmitted to the second circuit.

2. The semiconductor integrated circuit according to claim 1,

wherein a level converting circuit is provided for a signal line that transmits information between the first circuit and the second circuit,

wherein the level converting circuit comprises a clocked inverter circuit and a latch circuit, the clocked inverter circuit having an output terminal coupled to an input terminal of the latch circuit,

wherein the clocked inverter circuit comprises a series circuit having a pair of p-channel MOS transistors and a pair of n-channel MOS transistors,

wherein a signal is input to a common gate of one p-channel MOS transistor and one n-channel MOS transistor, a clock signal is supplied to a gate of the other p-channel MOS transistor, and an inverted clock signal of that clock signal is supplied to a gate of the other n-channel MOS transistor, and

wherein the latch circuit is latched in accordance with a cutoff state of the other p-channel MOS transistor and n-channel MOS transistor.

3. A semiconductor integrated circuit comprising:

a first circuit that operates using a first power-supply voltage supplied from a power supplying Large Scale Integration (LSI) circuit;

a second circuit that operates using a second power-supply voltage;

a clock generation circuit that generates a clock;

a clock tree that transmits the clock generated by the clock generation circuit to the first circuit and the second circuit;

a clock synchronization circuit having a plurality of delay stages that perform clock delay adjustment between a first path for transmitting the clock to the first circuit and a second path for transmitting the clock to the second circuit along the clock tree to synchronize the clock in the first and second paths; and

a control circuit that notifies the power supplying LSI circuit of change control over the first power-supply voltage,

wherein the power supplying LSI circuit is notified of a voltage change velocity for applying variable control to the first power-supply voltage,

wherein control is performed to match a phase between the clock as supplied to the first circuit and the clock as supplied to the second circuit when a voltage of the first circuit is changed at the voltage change velocity, and

wherein a first comparison circuit is a dynamic comparator that uses one clock signal as an activation signal for a differential input stage, differentially amplifies another clock signal based on a reference voltage equivalent to half a drive voltage for the another clock signal, and senses and latches a differential amplification result.

4. The semiconductor integrated circuit according to claim 3,

wherein a level converting circuit is provided for a signal line that transmits information between the first circuit and the second circuit,

wherein the level converting circuit comprises a clocked inverter circuit and a latch circuit, the clocked inverter circuit having an output terminal coupled to an input terminal of the latch circuit,

wherein the clocked inverter circuit comprises a series circuit having a pair of p-channel MOS transistors and a pair of n-channel MOS transistors,

wherein a signal is input to a common gate of one p-channel MOS transistor and one n-channel MOS transistor, a clock signal is supplied to a gate of the other p-channel MOS transistor, and an inverted clock signal of that clock signal is supplied to a gate of the other n-channel MOS transistor, and

wherein the latch circuit is latched in accordance with a cutoff state of the other p-channel MOS transistor and n-channel MOS transistor.

5. A semiconductor integrated circuit comprising:

a first circuit that operates using a first power-supply voltage supplied from a power supplying Large Scale Integration (LSI) circuit;

a second circuit that operates using a second power-supply voltage;

a clock generation circuit that generates a clock;

a clock tree that transmits the clock generated by the clock generation circuit to the first circuit and the second circuit;

a clock synchronization circuit having a plurality of delay stages that perform clock delay adjustment between a first path for transmitting the clock to the first circuit and a second path for transmitting the clock to the second circuit along the clock tree to synchronize the clock in the first and second paths; and

a control circuit that notifies the power supplying LSI circuit of change control over the first power-supply voltage,

wherein the power supplying LSI circuit is notified of a voltage change velocity for applying variable control to the first power-supply voltage,

wherein control is performed to match a phase between the clock as supplied to the first circuit and the clock as supplied to the second circuit when a voltage of the first circuit is changed at the voltage change velocity, and

wherein the first circuit comprises;

a clock gate circuit that selectively prevents the clock signal propagated along the clock tree from being output to a subsequent stage; and

a clock replica circuit that branches from the clock tree before the clock gate circuit and propagates the clock signal to simulate a clock delay from the clock gate circuit to a node, and

wherein a first phase comparison circuit compares a phase between a clock transmitted to the clock replica circuit and the clock transmitted to the second circuit.

6. A control method for clock signal synchronization that, in a semiconductor integrated circuit comprising a first circuit using a first power-supply voltage for operation and a second circuit using a second power-supply voltage for operation, performs clock delay adjustment between a first path for transmitting a clock to the first circuit and a second path for transmitting the clock to the second circuit along a clock tree for transmitting the clock to the first circuit and the second circuit and synchronizes the clock in the first and second paths, the method comprising:

a voltage change process of changing the first power-supply voltage using a control circuit; and

a clock synchronization process of controlling clock synchronization by performing the clock delay adjustment during the voltage change process,

wherein the semiconductor integrated circuit provides a clock synchronization circuit for a path for transmitting the clock to the first circuit,

wherein the clock synchronization circuit comprises;

a variable delay circuit for assigning a delay to an input clock signal;

a through path for letting the input clock signal pass through without assigning a delay; and

a selection circuit for selecting one of a clock signal output from the variable delay circuit and a clock signal output from the through path,

wherein the selection circuit selects the clock signal output from the through path when the first power-supply voltage is a standard voltage, and selects the clock signal output from the variable delay circuit when the first power-supply voltage is not a standard voltage.

7. The control method for clock signal synchronization according to claim 6,

wherein the clock synchronization process comprises:

a second comparison process of comparing a phase between the clock output signal from the variable delay circuit and the clock signal propagated along the through path;

using a comparison result from the second comparison process, performing a second delay setting process of setting a delay equivalent to an integral multiple of a clock cycle to an output from the variable delay circuit in accordance with the clock signal propagated along the through path; and

performing a first delay setting process comprising;

allowing the selection circuit to select the output from the variable delay circuit in response to an instruction to change the first power-supply voltage from the standard voltage to another voltage that is not the standard voltage,

adjusting a delay setting by the variable delay circuit based on a comparison result from a first comparison process, and

controlling phase synchronization between the clock transmitted to the first circuit and the clock transmitted to the second circuit.

8. A semiconductor integrated circuit comprising:

a first circuit that operates using a first power-supply voltage supplied from a power supplying Large Scale Integration (LSI) circuit;

a second circuit that operates using a second power-supply voltage;

a clock generation circuit that generates a clock;

a clock tree that transmits the clock generated by the clock generation circuit to the first circuit and the second circuit;

a clock synchronization circuit having a plurality of delay stages that perform clock delay adjustment between a first path for transmitting the clock to the first circuit and a second path for transmitting the clock to the second circuit along the clock tree to synchronize the clock in the first and second paths; and

a control circuit that notifies the power supplying LSI circuit of change control over the first power-supply voltage,

wherein the power supplying LSI circuit is notified of a voltage change velocity for applying variable control to the first power-supply voltage,

wherein control is performed to match a phase between the clock as supplied to the first circuit and the clock as supplied to the second circuit when a voltage of the first circuit is changed at the voltage change velocity, and

wherein the semiconductor integrated circuit branches the clock distributed to the second circuit into a third clock signal passing through a delay circuit and a fourth clock signal not passing through a delay circuit immediately before comparison with the clock for the first circuit, the semiconductor integrated circuit further comprising;

a third comparator that compares a phase between the clock distributed to the first circuit and the third clock signal;

a fourth phase comparator that compares a phase between the clock distributed to the first circuit and the fourth clock signal; and

a first delay stage change table,

wherein delay stage control is provided to control a delay variation at a next cycle and a comparison time interval for the third and fourth comparators at a next cycle, in accordance with a comparison result from the third and fourth phase comparators and data maintained in the first delay stage change table.

9. The semiconductor integrated circuit according to claim 8, wherein the delay stage control acquires information about starting or stopping a voltage change from a first external voltage regulator and, during a voltage change, changes the number of delay stages in accordance with a delay stage variation maintained in a second delay stage change table.

10. The semiconductor integrated circuit according to claim 9, further comprising:

a feature for determining whether or not a given phase difference is ensured between the third clock signal and the fourth clock signal,

wherein, when the difference is not ensured, the feature maintains chronological relative relation between the third and fourth clock signals as phase information in the second delay stage change table and corrects a delay stage variation maintained in the delay stage change table based on phase information maintained in the second delay stage change table.

11. The semiconductor integrated circuit according to claim 9, wherein the delay stage control acquires and controls information about starting or stopping a voltage change from a voltage sensor provided inside an LSI circuit.

12. The semiconductor integrated circuit according to claim 8, wherein the first and second circuits couple paths each having an equal latency up to clock tree nodes inside the circuits to first and second phase comparators.

13. The semiconductor integrated circuit according to claim 8, wherein the first and second circuits couple communicating paths to first and second phase comparators.