Liquid crystal display device and fabricating method thereof

• US 8,189,162 B2
• Filed: 05/27/2010
• Issued: 05/29/2012
• Est. Priority Date: 12/31/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Ahn, Byung Chul, Lim, Byoung Ho, Ahn, Jae Jun
• Primary Examiner(s): Nguyen, Lauren
• Application Number:
  US12/789,067
• Publication Number:
  US 20100237349A1
• Time in Patent Office: 733 Days
• Field of Search: 349/141, 349/138, 349/139, 349/149, 349/152
• US Class Current: 349/152
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence

Abstract

Disclosed is a thin film transistor substrate for a fringe filed switching type liquid crystal display device, and a fabrication method thereof, that reduces the number of required mask processes, and thus improves fabrication efficiency. The fabrication method involves three mask processes, wherein the masks are partial transmitting masks, and the resulting photo-resist patterns have varying thicknesses. By having photo-resist layers of varying thicknesses, structures can be formed in multiple etching steps using the same photo-resist pattern by incrementally removing the photo-resist according to its thickness. The thin film transistor substrate has a common line, a common electrode, a gate line and a gate electrode formed directly on the substrate. The common electrode overlaps the pixel electrode in the pixel area.

Claims

1. A liquid crystal display device, comprising:

first and second substrates;

a gate line on the first substrate;

a common line on the first substrate;

a common electrode on the first substrate, wherein the common electrode is connected to the common line;

a gate insulating film on the gate line, the common line, and the common electrode;

a data line on the gate insulating film, wherein the data line crosses the gate line;

a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode, and a semiconductor layer having a channel between the source electrode and the drain electrode;

a data pad having a transparent conductive layer in a contact hole passing through the gate insulating film, wherein the data line is extended to overlap with a portion of the contact hole and connected to the data pad by directly contacting on a portion of the data pad, and wherein the data pad forms an interface with the gate insulating film enclosing the contact hole; and

a pixel electrode formed directly on the gate insulating film connected to the drain electrode,

wherein one side of pixel electrode is aligned with one side of the semiconductor layer, and

wherein the drain electrode directly overlaps and directly contacts on a portion of the pixel electrode where the one side of the semiconductor layer and the one side of the pixel electrode are aligned.

2. The device of claim 1, wherein the common line includes:

a first layer having a transparent conductive material; and

a second layer having a metal.

3. The device of claim 2, wherein the first layer includes ITO.

4. The device of claim 2, wherein the second layer includes Mo.

5. The device of claim 2, wherein the common electrode is formed by an extension of the transparent conductive material of the common line.

6. The device of claim 1, wherein the pixel electrode overlaps the common electrode.

7. The device of claim 1, further comprising a gate pad connected to the gate line, wherein the gate pad includes:

a lower pad electrode on the first substrate; and

an upper pad electrode in a contact hole passing through the gate insulating film to expose the lower pad electrode,

wherein the upper pad electrode is connected to the lower pad electrode.

8. The device of claim 1,

wherein the data pad further includes:

a lower pad electrode provided on the first substrate; and

an upper pad electrode in a contact hole passing through the gate insulating film to expose the lower pad electrode,

wherein the upper pad electrode is connected to the lower pad electrode.

9. The device of claim 8, further comprising:

a data link extended from the lower pad electrode, wherein the data link overlaps the data line; and

a contact electrode in a second contact hole passing through the gate insulating film to expose the data link, wherein the contact electrode connects the data link to the data line.

10. The device of claim 1, wherein the channel between the source electrode and the drain electrode includes an oxidized surface.

11. The thin film transistor substrate of claim 1, further comprising a protective film on the first substrate.

12. The thin film transistor substrate of claim 11, further comprising an alignment film on the protective film.