Interface device for interfacing a main processor to processing engines and classifier engines, and methods for configuring and operating interface devices

• US 8,190,858 B2
• Filed: 02/25/2003
• Issued: 05/29/2012
• Est. Priority Date: 02/25/2003
• Status: Active Grant

• Current Assignee: Topside Research LLC
• Original Assignee: Topside Research LLC
• Inventors: Shui, Yaxin, Terry, Phil, Robertson, Kevin, Hong, Quang, Vuong, Bao K.
• Primary Examiner(s): LI, AIMEE J
• Application Number:
  US10/374,147
• Publication Number:
  US 20040168041A1
• Time in Patent Office: 3,381 Days
• Field of Search: 712/34, 712/33, 712/38, 709/305, 709/306, 709/307
• US Class Current: 712/34
• CPC Class Codes: G06F 13/12 using hardware independent of the central processor, e.g. channel or peripheral processor

Abstract

There is disclosed an interface device for interfacing between a main processor and one or more processing engines. The interface device is configurable, so that it may be used with a wide range of processing engines without being redesigned.

Claims

1. An interface device for interfacing a main processor and a processing engine, the interface comprising

a settings storage to store variables of the processing engine, the variables including

a translation of instructions into an operation code set of the processing engine

a conversion of operands into a format of the processing engine

a pin map of the processing engine

a clock rate of the processing engine

a main processor interface having a first pipe to couple to a first bus, the main processor interface to receive messages via the first bus from the main processor directed at the processing engine, wherein the first pipe has a fixed width, a fixed pin map and a fixed clock rate

a decoder coupled to the settings storage to

separate the messages into instructions and operands

translate the instructions to the operation code set of the processing engine according to the translation variable stored in the settings storage

convert the operands to the format of the processing engine according to the conversion variable stored in the settings storage

a processing engine interface having a second pipe to couple to a second bus, the processing engine interface to send translated operation codes and converted operands via the second bus to the processing engine, wherein the second pipe has a configurable pin map and a configurable clock rate to be used in conformance with the processing engine pin map and the processing engine clock rate.

2. The interface device of claim 1 wherein the decoder is further for configuring the processing engine interface to use the second pipe in conformance with the processing engine pin map and the processing engine clock rate.

3. The interface device of claim 1 further comprising a host processor interface coupled to the settings storage, the processing engine interface and a third pipe, the third pipe to couple to a third bus coupled to a host processor, wherein the third pipe has a fixed width, a fixed pin map and a fixed clock rate.

4. The interface device of claim 3, the host processor interface to receive third messages via the third pipe from the host processor for configuring the processing engine.

5. The interface device of claim 3, the host processor interface to receive third messages via the third pipe from the host processor for storing variables of the processing engine in the settings storage.

6. The interface device of claim 3, the host processor interface to receive third messages via the third pipe from the host processor for maintaining, initializing and debugging the processing engine.

7. The interface device of claim 1 wherein the main processor interface comprises a DMA interface.

8. The interface device of claim 7 wherein

the DMA interface includes the first pipe and the first pipe comprises a plurality of pipes

the DMA interface further includes a plurality of first-in, first-out memories (FIFOs) and an arbiter, the arbiter for directing messages from the plurality of pipes to the plurality of FIFOs based upon respective availability in the plurality of FIFOs for more messages.

9. The interface device of claim 8 wherein there is a one-to-one correspondence between the plurality of pipes and the plurality of FIFOs.

10. The interface device of claim 7 wherein the main processor interface comprises a fetcher comprising a plurality of register files and a controller for extracting instructions and data from the messages in the register files.

11. The interface device of claim 1 wherein the processing engine comprises a classifier engine, the interface further comprising a stitcher for prepending search results from the processor engine to instructions.

12. The interface device of claim 1 wherein the settings storage comprises a plurality of registers.

13. The interface device of claim 1 wherein the processing engine is selected from the group consisting of a single high speed and high density classifier engine, plural identical classifier engines, plural non-identical classifier engines, a classifier engine to receive its instruction through its data bus, a classifier engine to receive its operations code separate through its message data, a streaming pipelined memory, a content addressable memory (CAM), a ternary CAM, and a CAM with context SRAM.

14. The interface device of claim 1 wherein the interface device is included in an integrated circuit chip.

15. The interface device of claim 14 wherein the integrated circuit chip further comprises a DMA engine coupled to the interface device.

16. The interface device of claim 14 wherein the integrated circuit chip is included in a line card.

17. The interface device of claim 16 wherein the line card further comprises the main processor, a DMA engine coupled to the interface device, a host processor coupled to the interface device via a third bus, and the processing engine.

18. The interface device of claim 17 wherein the main processor and the DMA engine are on the integrated circuit chip.

19. The interface device of claim 16 wherein the processing engine comprises two processing engines, the interface device adapted for interfacing the main processor to the two processing engines independently and in parallel.

20. The interface device of claim 14 wherein the integrated circuit chip is included in a network device.

21. A method of configuring an interface device, the interface device for interfacing a main processor and a processing engine, the method comprising

providing the interface device, the interface device comprising a main processor interface and a processing engine interface

the main processor interface having a first pipe coupled to a first bus for receiving messages via the first bus from the main processor directed at the processing engine, wherein the first pipe has a fixed width, a fixed pin map and a fixed clock rate

the processing engine interface having a second pipe coupled to a second bus for sending translated instructions and converted operands via the second bus to the processing engine, wherein the second pipe has a configurable pin map and a configurable clock rate

storing variables of the processing engine, the variables including

a translation of instructions into an operation code set of the processing engine

a conversion of operands into a format of the processing engine

a pin map of the processing engine

a clock rate of the processing engine

using the second pipe in conformance with the processing engine pin map and the processing engine clock rate.

22. The method of claim 21 wherein a host processor, coupled to the interface device, provides the variables to the interface device.

23. The method of claim 21 further comprising a host processor, coupled to the interface device, to send messages to the interface device to configure the processing engine.

24. A method of operating an interface device, the interface device for interfacing a main processor and a processing engine, the method comprising

storing variables of the processing engine, the variables including

a translation of instructions into an operation code set of the processing engine

a conversion of operands into a format of the processing engine

a pin map of the processing engine

a clock rate of the processing engine

receiving messages via a first pipe in the interface device from the main processor directed at the processing engine, wherein the first pipe has a fixed width, a fixed pin map and a fixed clock rate

decoding the messages by

separating the messages into instructions and operands

translating the instructions to the instruction set of the processing engine according to the translation variable stored in the settings storage

converting the operands to the format of the processing engine according to the conversion variable stored in the settings storage

sending the translated operation codes and the converted operands via a second pipe in the interface device to the processing engine, wherein the second pipe has a configurable pin map and a configurable clock rate and is configured in conformance with the processing engine pin map and the processing engine clock rate.

25. The method of claim 24 wherein the step of receiving messages via a first pipe comprises receiving messages via a plurality of pipes into an arbiter, the arbiter directing messages from the plurality of pipes to a plurality of first-in, first-out memories (FIFOs).

26. The method of claim 25, wherein the arbiter directs messages to the FIFOs based upon respective availability in the plurality of FIFOs for more messages.

27. The method of claim 24 further comprising

receiving results from the processing engine

prepending the results from the processing engine to instructions.

28. An interface device for interfacing a main processor and a plurality of processing engines, the interface device comprising

a settings storage to store variables of the processing engines, respectively, the variables including

a translation of instructions into an operation code set of the processing engine

a conversion of operands from into a format of the processing engine

a pin map of the processing engine

a clock rate of the processing engine

a main processor interface having a first pipe to couple to a first bus, the main processor interface to receive messages via the first pipe from the main processor directed at the processing engines, wherein the first pipe has a fixed width, a fixed pin map and a fixed clock rate, the main processor interface further to identify which of the processing engines should receive the messages

a decoder coupled to the settings storage to

separate messages from the main processor into instructions and operands

translate the instructions from the instruction set of the main processor to the instruction set of the identified processing engine according to the translation variable stored in the settings storage for the identified processing engine

convert the operand from the format of the main processor to the format of the identified processing engine according to the conversion variable stored in the settings storage for the identified processing engine

a processing engine interface having plural second pipes to respectively coupled to plural second buses, the processing engine interface to send translated operation codes and converted operands via the second buses to the identified processing engines, wherein the second pipes have configurable pin maps and configurable clock rates configurable to be used in conformance with the processing engine pin map and the processing engine clock rate for the respective processing engines.

29. The interface device of claim 28 wherein the decoder includes logic for independently and in parallel separating, translating and converting the messages for the respective processing engines.

30. The interface device of claim 28 wherein the main processor interface is further to identify which of the processing engines should receive each message based upon how busy the processing engines are.

31. The interface device of claim 28 wherein the decoder is further to configure the processing engine interface to use the second pipes in conformance with the processing engine pin maps and the processing engine clock rates.

32. The interface device of claim 28 wherein the processing engines are identical.

33. The interface device of claim 28 wherein the processing engines are different.

34. The interface device of claim 33 wherein the integrated circuit chip is included in a line card.

35. The interface device of claim 34 wherein the integrated circuit chip further comprises the main processor a DMA engine coupled to the interface device via the first bus, and the processing engines.

36. The interface device of claim 35 wherein the main processor and the DMA engine are on the integrated circuit chip.

37. The interface device of claim 28 wherein the interface device is included in an integrated circuit chip.

38. The interface device of claim 37 wherein the integrated circuit chip is included in a network device.

39. A method of operating an interface device, the interface device for interfacing a main processor and a plurality of processing engines, the method comprising

storing variables of the processing engines, the variables respectively including

a translation of instructions into an operation code set of the processing engine

a conversion of operands into a format of the processing engine

a pin map of the processing engine

a clock rate of the processing engine

receiving messages via a first pipe in the interface device from the main processor, wherein the first pipe has a fixed width, pin map and clock rate

identifying which of the processing engines should receive the messages

decoding the messages by

separating the messages into instructions and operands

translating the instructions to the operation code set of the identified processing engine according to the translation variable stored in the settings storage for the identified processing engine

converting the operands to the format of the identified processing engine according to the conversion variable stored in the settings storage for the identified processing engine

sending the translated operation codes and the converted operands via plural second pipes in the interface device to the identified processing engines, wherein the second pipes have configurable pin maps and configurable clock rates and are configured in conformance with the processing engine pin map and the processing engine clock rate of the respective processing engines.

40. The method of claim 39 wherein the step of receiving messages via a first pipe comprises receiving messages via a plurality of pipes into an arbiter, the arbiter directing messages from the plurality of pipes to a plurality of first-in, first-out memories (FIFOs).

41. The method of claim 40, wherein the arbiter directs messages to the FIFOs based upon respective availability in the plurality of FIFOs for more messages.

42. The method of claim 39 further comprising

receiving results from the processing engine to the translated instructions and the converted operands

prepending the results from the processing engine to a prior result from the processing engine.

43. The method of claim 39 further comprising independently and in parallel separating, decoding the messages for the respective processing engines.

44. The method of claim 39 wherein the identifying step comprises determining how busy the processing engines are and selecting a one of the processing engines based upon how busy the processing engines are.