Silicon carbide semiconductor device including deep layer

• US 8,193,564 B2
• Filed: 02/12/2009
• Issued: 06/05/2012
• Est. Priority Date: 02/13/2008
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Suzuki, Naohiro, Okuno, Eiichi, Matsuki, Hideo
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): TRAN, TRANG Q
• Application Number:
  US12/379,076
• Publication Number:
  US 20090200559A1
• Time in Patent Office: 1,209 Days
• Field of Search: 257/216, 257/219, 257328-331, 257/341, 257/E29.201
• US Class Current: 257/216
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A silicon carbide semiconductor device includes a substrate, a drift layer located on a first surface of the substrate, a base region located on the drift layer, a source region located on the base region, a trench penetrating the source region and the base region to the drift layer, a channel layer located in the trench, a gate insulating layer located on the channel layer, a gate electrode located on the gate insulating layer, a source electrode electrically coupled with the source region and the base region, a drain electrode located on a second surface of the substrate, and a deep layer. The deep layer is located under the base region, extends to a depth deeper than the trench and is formed along an approximately normal direction to a sidewall of the trench.

Claims

1. A silicon carbide semiconductor device comprising a plurality of MOSFETs arranged in a first direction and a plurality of deep layers, each of the plurality of MOSFETs including:

a substrate made of silicon carbide, the substrate having a first conductivity type, the substrate having first and second opposing surfaces;

a drift layer located on the first surface of the substrate, the drift layer made of silicon carbide, the drift layer having the first conductivity type and having an impurity concentration less than an impurity concentration of the substrate;

a base region located on the drift layer, the base region made of silicon carbide and having a second conductivity type;

a source region located on the base region, the source region made of silicon carbide, the source region having the first conductivity type and having an impurity concentration greater than the impurity concentration of the drift layer;

a trench extending to a depth deeper than the source region and the base region and reaching the drift layer, the trench sandwiched by each of the base region and the source region, the trench provided along a second direction, the second direction intersecting with the first direction in a planar direction of the substrate;

a gate insulating layer located on a surface of the trench;

a gate electrode located on the gate insulating layer in the trench;

a source electrode electrically coupled with the source region and the base region;

a drain electrode located on the second surface of the substrate; and

a body layer having a predetermined distance from a sidewall of the trench, the body layer located at a portion deeper than the source region, the body layer having the second conductivity type and having an impurity concentration greater than the impurity concentration of the base region, wherein

the plurality of deep layers has a stripe shape formed in parallel with the planar direction of the substrate along the first direction,

the plurality of deep layers is located under each base region in the plurality of MOSFETs, has a constant depth, and extends to a depth deeper than each trench in the plurality of MOSFETs,

the plurality of deep layers has the second conductivity type,

the plurality of deep layers intersects with each trench in the plurality of MOSFETs in a lattice pattern, and

in each of the plurality of MOSFETs, an inversion channel is provided at a surface portion of the base region located on the sidewall of the trench and electric current flows between the source electrode and the drain electrode through the source region and the drift layer by controlling a voltage applied to the gate electrode.

2. The silicon carbide semiconductor device according to claim 1, further comprising one or more of the deep layers, wherein:

each of the deep layers has a width of about 1.5 μ

m;

the deep layers are arranged at intervals of about 2.0 μ

m; and

the predetermined distance from the sidewall of the trench and the body layer is between about 0.4 μ

m and about 0.9 μ

m.

3. The silicon carbide semiconductor device according to claim 1, wherein the impurity concentration of the base region is between about 5.0×

10¹⁵ cm<sup>−

3</sup> and about 5.0×

10¹⁶ cm<sup>−

3</sup>; and

the impurity concentration of the body layer is between about 1.0×

10¹⁸ cm<sup>−

3</sup> and about 1.0×

10²⁰ cm<sup>−

3</sup>.