Self-calibrating gain control system

• US 8,198,940 B2
• Filed: 05/04/2010
• Issued: 06/12/2012
• Est. Priority Date: 05/04/2009
• Status: Active Grant

• Current Assignee: Maxlinear Incorporated
• Original Assignee: Maxlinear Incorporated
• Inventors: Qiu, James, Ramesh, Sridhar
• Primary Examiner(s): Mottola, Steven J
• Application Number:
  US12/799,870
• Publication Number:
  US 20100277240A1
• Time in Patent Office: 770 Days
• Field of Search: 330/133, 330/140, 330/279
• US Class Current: 330/133
• CPC Class Codes: H03G 3/20 Automatic control H03G3/005 takes precedence; combined with volume compression or expansion H03G7/00
• CPC Class Codes: H03G 3/3052 in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence

Abstract

A circuit for self-calibrating a gain control system samples the output of a digital amplifier coupled in series with one or more analog amplifiers to correct errors in a discrete stepped gain control. A digital gain control circuit controls both the digital amplifier and at least one analog amplifier to produce a smooth linear and continuous gain, wherein perturbations in the digital control of gain are smoothed by a signal applied to gain control circuit by a gain step correction circuit.

Claims

1. A step gain control system, comprising:

an analog amplifier for receiving an analog input signal;

a digital signal amplifier cascaded with said analog amplifier through an analog to digital converter (ADC) to produce an output signal;

a gain control circuit;

a signal detector;

a gain step correction circuit; and

said gain control circuit applies a gain adjustment to the analog amplifier and the digital signal amplifier in incremental steps, wherein the signal detector detects an output signal of the digital signal amplifier and connects a signal to the gain step correction circuit.

2. The system of claim 1, wherein said analog amplifier is an RF low noise amplifier.

3. The system of claim 1, wherein said signal detector is a root-mean-square signal detector.

4. The system of claim 1, wherein said signal detector is an estimator of signal level comprising a peak/envelope/power detector.

5. The system of claim 1, wherein said gain step correction circuit maintains previous RMS detections of the output signal and produces a filtering of the previous and present RMS detections that is connected to the gain step correction circuit as a correction signal.

6. The system of claim 5, wherein said filtering is an averaging function.

7. The system of claim 1, wherein said analog amplifier is controlled by the gain control circuit using digital signals.

8. The system of claim 1, wherein said gain adjustment increases with falling analog input signal and decreases with raising analog input signal.

9. A method of gain control, comprising:

coupling an analog amplifier in series with a digital amplifier;

controlling gain of the analog amplifier and the digital amplifier with a digital gain control circuit;

detecting an output of the digital amplifier with signal detector;

coupling an output of the signal detector to a gain step correction circuit;

averaging the output with previous output of the signal detector to produce an error correction signal coupled to the digital gain control circuit, wherein said digital gain control circuit applies gain adjustments to the analog amplifier in discrete steps and to the digital amplifier in continuous steps.

10. The method of claim 9, wherein said analog amplifier is an RF low noise amplifier.

11. The method of claim 9, wherein said signal detector is a root-mean-square signal detector.

12. The method of claim 9, wherein said signal detector is an estimator of signal level comprising one of the following signal detectors:

a peak detector;

an envelope detector; and

a power detector.

13. The method of claim 9, wherein said step correction circuit maintains previous detections of the output signal of the digital amplifier and produces a filtering of the previous and present detection of the digital amplifier to form an error correction signal to be connected to the gain step correction circuit.

14. The method of claim 13, wherein said filtering is an averaging function.

15. The method of claim 9, wherein said analog amplifier is controlled by the gain control circuit using digital signals.

16. The method of claim 9, wherein said gain adjustment increases with falling analog input signal and decreases with raising analog input signal.

17. A system for wireless communication, the method comprising:

a radio frequency (RF) receiver comprising one or more analog amplifiers, an analog-to-digital converter (ADC), one or more digital amplifiers having a signal detector at an output of said one or more digital amplifiers, a gain control circuit, and a gain step correction circuit, wherein said gain control circuit is operable to apply gain adjustments to said one or more analog amplifiers and said one or more digital amplifiers in incremental steps, said gain adjustments being based on detections by said signal detector at said output of said one or more digital amplifiers received by said gain step correction circuit.

18. The system according to claim 17, wherein said received detections comprise stored and present RMS detections of said output of said one or more digital amplifiers.

19. The system according to claim 18, wherein said gain step correction circuit filters said stored and present detections.

20. The system according to claim 17, wherein said signal detector comprises one or more of:

a peak detector, an envelope detector, and a power detector.