Semiconductor device

• US 8,199,551 B2
• Filed: 09/30/2009
• Issued: 06/12/2012
• Est. Priority Date: 10/02/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Matsuzaki, Takanori
• Primary Examiner(s): NGUYEN, DANG T
• Application Number:
  US12/570,619
• Publication Number:
  US 20100085792A1
• Time in Patent Office: 986 Days
• Field of Search: 365/72, 365/149, 365/175, 365/105, 365/49, 365/187, 365/189.09, 365/189.05, 365/201, 365/229, 365/226, 365/227, 365/172, 365/156
• US Class Current: 365/72
• CPC Class Codes: G11C 11/4023 using field effect transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

A semiconductor device including a memory cell is provided. The memory cell comprises a transistor and a capacitor, and one of a resistor and a diode. A gate of the transistor is electrically connected to a word line, and one of a source and a drain of the transistor is electrically connected to a bit line. One terminal of the capacitor is electrically connected to the other of the source and the drain of the transistor, and the other terminal of the capacitor is electrically connected to a wiring. One terminal of one of the resistor and the diode is electrically connected to the other of the source and the drain of the transistor, and the other terminal of one of the resistor and the diode is electrically connected to the wiring.

Claims

1. A semiconductor device including a memory cell, the memory cell comprising:

a transistor, a gate of the transistor being electrically connected to a word line, and one of a source and a drain of the transistor being electrically connected to a bit line;

a capacitor, one terminal of the capacitor being electrically connected to the other of the source and the drain of the transistor, and the other terminal of the capacitor being electrically connected to a wiring; and

a resistor, one terminal of the resistor being electrically connected to the other of the source and the drain of the transistor, and the other terminal of the resistor being electrically connected to the wiring,

wherein, when a potential of the gate of the transistor and a potential of the one of the source and the drain of the transistor is equal to a potential of the other terminal of the capacitor, an amount of electric charge which is discharged from the capacitor and flows to the resistor is larger than an amount of electric charge which is discharged from the capacitor and flows to the transistor.

2. The semiconductor device according to claim 1, further comprising a buffer circuit electrically connected to the other of the source and the drain of the transistor.

3. The semiconductor device according to claim 1, further comprising an antenna circuit which transmits/receives a signal wirelessly, and wherein the memory cell is kept data based on the signal.

4. A semiconductor device including a memory cell, the memory cell comprising:

a transistor, a gate of the transistor being electrically connected to a word line, and one of a source and a drain of the transistor being electrically connected to a bit line;

a capacitor, one terminal of the capacitor being electrically connected to the other of the source and the drain of the transistor, and the other terminal of the capacitor being electrically connected to a wiring; and

a diode, one terminal of the diode being electrically connected to the other of the source and the drain of the transistor, and the other terminal of the diode being electrically connected to the wiring,

wherein, when a potential of the gate of the transistor and a potential of the one of the source and the drain of the transistor is equal to a potential of the other terminal of the capacitor, an amount of electric charge which is discharged from the capacitor and flows to the diode is larger than an amount of electric charge which is discharged from the capacitor and flows to the transistor.

5. The semiconductor device according to claim 4, further comprising a buffer circuit electrically connected to the other of the source and the drain of the transistor.

6. The semiconductor device according to claim 4, further comprising an antenna circuit which transmits/receives a signal wirelessly, and wherein the memory cell is kept data based on the signal.

7. The semiconductor device according to claim 4, wherein the diode is a second transistor, and wherein a gate of the second transistor is electrically connected to one of a source and a drain of the second transistor.

8. A semiconductor device including a memory cell, the memory cell comprising:

a transistor, a gate of the transistor being electrically connected to a word line, and one of a source and a drain of the transistor being electrically connected to a bit line;

a capacitor, one terminal of the capacitor being electrically connected to the other of the source and the drain of the transistor, and the other terminal of the capacitor being electrically connected to a wiring; and

a resistor, one terminal of the resistor being electrically connected to the other of the source and the drain of the transistor, and the other terminal of the resistor being electrically connected to the wiring,

wherein an electric charge discharged from the capacitor is capable of flowing to the transistor and the resistor, and

wherein, when a potential of the gate of the transistor and a potential of the one of the source and the drain of the transistor is equal to a potential of the other terminal of the capacitor an amount of electric charge which is discharged from the capacitor and flows to the resistor is larger than an amount of electric charge which is discharged from the capacitor and flows to the transistor.

9. The semiconductor device according to claim 8, further comprising a buffer circuit electrically connected to the other of the source and the drain of the transistor.

10. The semiconductor device according to claim 8, further comprising an antenna circuit which transmits/receives a signal wirelessly, and wherein the memory cell is kept data based on the signal.

11. A semiconductor device including a memory cell, the memory cell comprising:

a transistor, a gate of the transistor being electrically connected to a word line, and one of a source and a drain of the transistor being electrically connected to a bit line;

a capacitor, one terminal of the capacitor being electrically connected to the other of the source and the drain of the transistor, and the other terminal of the capacitor being electrically connected to a wiring; and

a diode, one terminal of the diode being electrically connected to the other of the source and the drain of the transistor, and the other terminal of the diode being electrically connected to the wiring,

wherein an electric charge discharged from the capacitor is capable of flowing to the transistor and the diode, and

wherein, when a potential of the gate of the transistor and a potential of the one of the source and the drain of the transistor is equal to a potential of the other terminal of the capacitor, an amount of electric charge which is discharged from the capacitor and flows to the diode is larger than an amount of electric charge which is discharged from the capacitor and flows to the transistor.

12. The semiconductor device according to claim 11, further comprising a buffer circuit electrically connected to the other of the source and the drain of the transistor.

13. The semiconductor device according to claim 11, further comprising an antenna circuit which transmits/receives a signal wirelessly, and wherein the memory cell is kept data based on the signal.

14. The semiconductor device according to claim 11, wherein the diode is a second transistor, and wherein a gate of the second transistor is electrically connected to one of a source and a drain of the second transistor.