Method and apparatus for providing protected intellectual property

• US 8,200,472 B1
• Filed: 01/20/2010
• Issued: 06/12/2012
• Est. Priority Date: 04/26/2000
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Molson, Philippe, San, Tony
• Primary Examiner(s): Thangavelu, Kandasamy
• Application Number:
  US12/690,781
• Time in Patent Office: 874 Days
• Field of Search: 703/13, 703/14, 703/22, 713/189, 716/100, 716/106, 326/37, 326/41, 326/38, 710/9, 365/201, 365/20
• US Class Current: 703/14
• CPC Class Codes: G06F 2115/08 Intellectual property [IP] blocks or IP cores
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06Q 40/08 Insurance

Abstract

Various techniques permit more thorough development of digital systems and devices by designers while protecting the proprietary interests of the owners of the intellectual property incorporated in such systems and devices. More specifically, the present invention provides to an end customer IP hardware which is suitable for prototype testing, but unusable for production purposes. One method limits the physical or electrical mode of operation of a hardware platform used for prototype testing of intellectual property (such as limiting the number of electrical contacts between the hardware and an external electrical device or limiting the data format(s) usable in the hardware during prototype testing). Another method limits the temporal operation of a hardware platform using an internal counter within the software provided by the intellectual property owner. Once a clock count limit is reached, the software disables the hardware in one or more prescribed ways, such as a reset of one or more registers, a global tri-state of the hardware IO, or a random failure of some type. Suitable hardware fabrication and/or augmentation also may be used to differentiate between the prototype and production manners of operation.

Claims

1. A method, comprising:

identifying license information associated with a logic function for implementation on a programmable logic device;

based on said identifying, determining whether the logic function should be implemented with a mode of operation restriction from a plurality of mode of operation restrictions, wherein the plurality of mode of operation restrictions include physical and electrical mode of operation restrictions; and

implementing the logic function on the programmable logic device, wherein operation of the logic function on the programmable logic device is limited as defined by the mode of operation restriction and in response to determining that said logic function should be implemented with said mode of operation restriction.

2. The method of claim 1, wherein the logic function is implemented with the mode of operation restriction as defined by license information.

3. The method of claim 1, wherein the mode of operation restriction is applied by disabling the logic function when an unallowed data format is received.

4. The method of claim 1, wherein the mode of operation restriction is applied by disabling a plurality of electrical contacts associated with the programmable logic device.

5. The method of claim 1, wherein the mode of operation restriction is applied by generating a random failure.

6. The method of claim 1, wherein the mode of operation restriction is applied by initiating a global tristate of hardware I/O.

7. The method of claim 1, wherein mode of operation restrictions are applied after a predetermined period of time.

8. The method of claim 1, wherein an internal clock of the programmable logic device is used for measuring run time.

9. The method of claim 1, wherein a predetermined period of time corresponds to a prototype operation range.

10. The method of claim 1, wherein a predetermined period of time corresponds to a production operation range.

11. A system, comprising:

an interface operable to receive license information associated with a logic function for implementation on a programmable logic device; and

a processor operable to determine that the logic function should be implemented with a mode of operation restriction from a plurality of mode of operation restrictions, wherein the plurality of mode of operation restrictions include physical and electrical mode of operation restrictions, wherein the processor is further operable to implement the logic function on the programmable logic device, wherein operation of the logic function on the programmable logic device is limited as defined by the mode of operation restriction and in response to determining that said logic function should be implemented with said mode of operation restriction.

12. The system of claim 11, wherein the logic function is implemented with the mode of operation restriction specified by license information.

13. The system of claim 11, wherein the mode of operation restriction is applied by disabling the logic function when an unallowed data format is received.

14. The system of claim 11, wherein the mode of operation restriction is applied by disabling a plurality of electrical contacts associated with the programmable logic device.

15. The system of claim 11, wherein the mode of operation restriction is applied by generating a random failure.

16. A programmable logic device, comprising:

a logic function implemented on the programmable logic device with a mode of operation restriction from a plurality of mode of operation restrictions, the logic function associated with license information;

wherein a plurality of mode of operation restrictions include physical and electrical mode of operation restrictions, wherein the mode of operation restriction is applied after a predetermined period of time.

17. The programmable logic device of claim 16, wherein the logic function is implemented with the mode of operation restriction specified by license information.

18. The programmable logic device of claim 16, wherein the mode of operation restriction is applied by disabling the logic function when an unallowed data format is received.

19. The programmable logic device of claim 16, wherein the mode of operation restriction is applied by disabling a plurality of electrical contacts associated with the programmable logic device.

20. The programmable logic device of claim 16, wherein the mode of operation restriction is applied by generating a random failure.