Circuit

• US 8,207,976 B2
• Filed: 03/21/2007
• Issued: 06/26/2012
• Est. Priority Date: 03/15/2007
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Hein, Thomas
• Primary Examiner(s): Washburn, Daniel
• Application Number:
  US11/726,401
• Publication Number:
  US 20080225603A1
• Time in Patent Office: 1,924 Days
• Field of Search: 345/519, 365/194, 365/233.1, 327/158, 714/798, 713/400, 713/401, 713/500, 713/503, 711/167, 375/354
• US Class Current: 345/519
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1093 Input synchronization

Abstract

An embodiment of a circuit includes an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.

Claims

1. A circuit comprising:

an output buffer comprising an input and an output;

a data interface for transmitting and receiving data, the data interface being coupled to the output of the output buffer;

a command/address interface coupled to the input of the output buffer;

a memory core coupled to the input of the output buffer;

a second output buffer comprising an input and an output, the output of the second output buffer being coupled to the data interface or to a further output pin;

an EDC circuit having an output coupled to the input of the second output buffer; and

a controller circuit adapted to cause data stored within the output buffer to be output to the data interface upon reception of a first signal, further adapted to cause data stored within the memory core to be output to the input of the output buffer upon reception of a second signal so that the data is stored within the output buffer, further adapted to cause provision of data received at the command/address interface via an address portion thereof to the input of the output buffer upon reception of a third signal so that the data is stored within the output buffer, further adapted to cause data which is stored within the second output buffer to be output to the data interface or the further output pin, further being adapted to cause data which is provided by the EDC circuit to be stored within the second output buffer, and further being adapted to cause data which is received at the command/address interface to be stored within the second output buffer.

2. The circuit as claimed in claim 1, further comprising a temporary memory coupled between the command/address interface and the output buffer and adapted to allow temporary storage of the data received at the command/address interface.

3. The circuit as claimed in claim 1, further comprising a data bus with at least one signal line between the memory core and the input of the output buffer.

4. The circuit as claimed in claim 3, further comprising a demultiplexer connected between the data bus and the command/address interface and adapted to couple data which is received at the command/address interface into the data bus as a function of an addressing signal.

5. The circuit as claimed in claim 4, wherein the demultiplexer is adapted to to be addressed via signal lines of the command/address interface.

6. The circuit as claimed in claim 1, wherein the output buffer is adapted to simultaneously buffer a larger amount of data than is simultaneously receivable via the command/address interface.

7. The circuit as claimed in claim 1, wherein the output buffer is adapted to simultaneously store 72 bits or 80 bits, and the command/address interface is adapted to simultaneously receive 9 bits or 10 bits.

8. The circuit as claimed in claim 1, wherein the circuit further comprises a plurality of output buffers, each having an input and an output, each coupled to the memory core via the respective input, each coupled to the data interface via the respective output, and each coupled to the command/address interface via the respective input, the circuit being adapted to cause the data which is received at the command/address interface to be stored within each of the output buffers of the plurality of output buffers.

9. The circuit as claimed in claim 1, wherein the circuit is a GDDRx memory circuit, x designating a GDDR standard.

10. The circuit as claimed in claim 1, wherein the circuit is a DRAM memory circuit.

11. The circuit as claimed in claim 1, wherein the EDC circuit calculates a check value or a check sum that is used to identify data errors.

12. The circuit as claimed in claim 1, wherein the output buffer is a FIFO buffer and the second output buffer is a FIFO buffer.

13. A circuit comprising:

an output buffer comprising an input and an output;

a data interface which is at least in a position to transmit data, the data interface being coupled to the output of the output buffer;

a command/address interface coupled to the input of the output buffer;

a memory core coupled to the input of the output buffer;

a controller circuit adapted to cause data stored within the output buffer to be output to the data interface upon reception of a first signal, further adapted to cause data stored within the memory core to be output to the input of the output buffer upon reception of a second signal so that the data is stored within the output buffer, and further adapted to cause provision of data received at the command/address interface to the input of the output buffer upon reception of a third signal so that the data is stored within the output buffer; and

further comprising a processing circuit and a second output buffer comprising an input and an output, the processing circuit being coupled to the input of the second output buffer, the output of the second output buffer being coupled to the data interface or a further pin, and the controller circuit being adapted to cause data which is stored within the second output buffer to be output to the data interface or the further pin, the controller circuit further being adapted to cause data which is provided by the processing circuit to be stored within the second output buffer, and the controller circuit further being adapted to cause data which is received at the command/address interface to be stored within the second output buffer.

14. The circuit as claimed in claim 13, further comprising a second temporary memory connected between the command/address interface and the input of the second output buffer, and adapted to enable temporary storage of at least part of the data coming in at the command/address interface.

15. The circuit as claimed in claim 14, wherein the processing circuit is coupled to the input of the second output buffer via a second bus, wherein the second bus comprises at least one signal line.

16. The circuit as claimed in claim 15, further comprising a demultiplexer coupled between the second bus and the command/address interface, and adapted to couple the data which is received at the command/address interface into the bus as a function of the addressing signal or of a further addressing signal.

17. The circuit as claimed in claim 16, wherein the demultiplexer is adapted to be addressed via signal lines of the command/address interface.

18. The circuit as claimed in claim 14, wherein the memory circuit is adapted to enable the first or second temporary memory to be addressed via signal lines of the command/address interface.

19. The circuit as claimed in claim 13, wherein the second output buffer is adapted to buffer a larger amount of data than may be provided at the same time to the second output buffer via the command/address interface.

20. The circuit as claimed in claim 13, wherein the second output buffer is adapted to buffer 8 bits in each case, and the circuit further being adapted to provide less than 8 bits to the second output buffer at any one time.

21. The circuit as claimed in claim 13, wherein the processing circuit is an EDC circuit adapted to calculate a check sum on the basis of data provided to the processing circuit.

22. The circuit as claimed in claim 13, wherein the circuit further comprises a plurality of output buffers, each having an input and an output, each coupled to the memory core via the respective input, each coupled to the data interface via the respective output, and each coupled to the command/address interface via the respective input, the circuit being adapted to cause the data which is received at the command/address interface to be stored within each of the output buffers of the plurality of output buffers.

23. The circuit as claimed in claim 13, wherein the circuit is a GDDRx memory circuit, x designating a GDDR standard.

24. The circuit as claimed in claim 13, wherein the circuit is a DRAM memory circuit.

25. A circuit comprising:

an output buffer comprising an input and an output;

a data interface adapted to allow the transmission and reception of data, the data interface being coupled to the output of the output buffer;

a command/address interface having signal lines for receiving at least an address signal and a further address signal;

a memory core;

a bus coupling the memory core to the input of the output buffer, the bus comprising a plurality of signal lines

a demultiplexer coupling the command/address interface to the bus such that data received at the command/address interface may be coupled into the bus as a function of the address signal or the further address signal;

a second output buffer comprising an input and an output, the output of the second output buffer being coupled to the data interface or to a further output pin;

an EDC circuit having an output coupled to the input of the second output buffer; and

a controller circuit adapted to cause data stored within the output buffer to be output to the data interface upon reception of a first signal, further adapted to cause data stored within the memory core to be output to the input of the output buffer upon reception of a second signal so that the data is stored within the output buffer, further adapted to cause provision of data received at the command/address interface via an address portion thereof to the input of the output buffer upon reception of a third signal so that the data is stored within the output buffer, further adapted to cause data which is stored within the second output buffer to be output to the data interface or the further output pin, further being adapted to cause data which is provided by the EDC circuit to be stored within the second output buffer, and further being adapted to cause data which is received at the command/address interface to be stored within the second output buffer.

26. The circuit as claimed in claim 25, wherein the circuit further comprises a plurality of output buffers, each having an input and an output, each coupled to the memory core via the respective input, each further coupled to the data interface via the respective output, and each further coupled to the command/address interface via the respective input, the circuit being adapted to cause the data which is received at the command/address interface to be stored within each of the output buffers of the plurality of output buffers.

27. The circuit as claimed in claim 26, wherein the circuit is a GDDRx memory circuit, x designating a GDDR standard.

28. The circuit as claimed in claim 27, wherein the circuit is a DRAM memory circuit.

29. The circuit as claimed in claim 26, wherein the circuit is a DRAM memory circuit.

30. The circuit as claimed in claim 25, wherein the circuit is a GDDRx memory circuit, x designating a GDDR standard.

31. The circuit as claimed in claim 25, wherein the circuit is a DRAM memory circuit.

32. A circuit comprising:

an output buffer comprising an input and an output;

a data interface adapted to allow at least the transmission of data, the data interface being coupled to the output of the output buffer;

a command/address interface having signal lines for receiving at least an address signal and a further address signal;

a memory core;

a bus coupling the memory core to the input of the output buffer, the bus comprising a plurality of signal lines;

a demultiplexer coupling the command/address interface to the bus such that data received at the command/address interface may be coupled into the bus as a function of the address signal or the further address signal;

a controller circuit adapted to cause data stored within the output buffer to be output to the data interface upon reception of a signal, further adapted to cause data stored within the memory core to be output to the input of the output buffer upon reception of a second signal so that the data is stored within the output buffer, and further adapted to cause provision of data received at the command/address interface to the input of the output buffer upon reception of a third signal so that the data is stored within the output buffer;

an EDC circuit;

a second output buffer comprising an input and an output;

a second bus comprising a plurality of signal lines and the second bus coupling the EDC circuit to the input of the second output buffer; and

a demultiplexer coupling the command/address interface to the second bus such that at least part of the data received at the command/address interface may be coupled into the second bus on the basis of the address signal or the further address signal,

the output of the second output buffer being coupled to the data interface or to a further pin.

33. The circuit as claimed in claim 32, wherein the circuit is a GDDRx memory circuit, x designating a GDDR standard.

34. The circuit as claimed in claim 32, wherein the circuit is a DRAM memory circuit.

35. A memory system comprising:

a memory circuit comprising

an output buffer comprising an input and an output;

a data interface for transmitting and receiving data, the data interface being coupled to the output of the output buffer;

a command/address interface coupled to the input of the output buffer;

a memory core coupled to the input of the output buffer;

a second output buffer comprising an input and an output, the output of the second output buffer being coupled to the data interface or to a further output pin;

an EDC circuit having an output coupled to the input of the second output buffer; and

a controller circuit adapted to cause data stored within the output buffer to be output to the data interface upon reception of a first signal, further adapted to cause data stored within the memory core to be output to the input of the output buffer upon reception of a second signal so that the data is stored within the output buffer, further adapted to cause provision of data received at the command/address interface via an address portion thereof to the input of the output buffer upon reception of a third signal so that the data is stored within the output buffer, further adapted to cause data which is stored within the second output buffer to be output to the data interface or the further output pin, further being adapted to cause data which is provided by the EDC circuit to be stored within the second output buffer, and further being adapted to cause data which is received at the command/address interface to be stored within the second output buffer; and

a memory controller comprising

a command/address interface;

a data interface; and

a synchronization circuit coupled to the command/address interface and to the data interface, and adapted to output a transmit data pattern as the synchronization data on the command/address interface via an address portion thereof, further adapted to receive a receive data pattern from the data interface, and further adapted to perform a training operation on the data interface on the basis of the transmit data pattern and the receive data pattern, the transmit data pattern selected to perform one of a symbol training operation and a frame synchronization operation,

the data interface of the memory circuit, and the data interface of the memory controller being coupled to one another, and

the command/address interface of the memory circuit being coupled to the command/address interface of the memory controller.

36. A graphics system comprising:

a GDDRx memory circuit, x being a number and designating a GDDR standard, the memory circuit comprising

an output buffer comprising an input and an output;

a data interface for transmitting and receiving data, the data interface being coupled to the output of the output buffer;

a command/address interface coupled to the input of the output buffer;

a memory core coupled to the input of the output buffer;

a second output buffer comprising an input and an output, the output of the second output buffer being coupled to the data interface or to a further output pin;

an EDC circuit having an output coupled to the input of the second output buffer; and

a controller circuit adapted to cause data stored within the output buffer to be output to the data interface upon reception of a signal, further adapted to cause data stored within the memory core to be output to the input of the output buffer upon reception of a second signal so that the data is stored within the output buffer, and further adapted to cause provision of data received at the command/address interface via an address portion thereof to the input of the output buffer upon reception of a third signal so that the data is stored within the output buffer, further adapted to cause data which is stored within the second output buffer to be output to the data interface or the further output pin, further being adapted to cause data which is provided by the EDC circuit to be stored within the second output buffer, and further being adapted to cause data which is received at the command/address interface to be stored within the second output buffer; and

a GPU comprising

a command/address interface;

a data interface; and

a synchronization circuit coupled to the command/address interface and to the data interface, and adapted to output a transmit data pattern as the synchronization data_on the command/address interface via an address portion thereof, further adapted to receive a receive data pattern from the data interface, and further adapted to perform a training operation on the data interface on the basis of the transmit data pattern and the receive data pattern, the transmit data pattern selected to perform one of a symbol training operation and a frame synchronization operation,

the data interface of the GDDRx memory circuit, and the data interface of the GPU being coupled to one another, and

the command/address interface of the GDDRx memory circuit being coupled to the command/address interface of the GPU.