Methods and systems for computer aided design of 3D integrated circuits

• US 8,209,649 B2
• Filed: 08/07/2009
• Issued: 06/26/2012
• Est. Priority Date: 07/26/2005
• Status: Active Grant

• Current Assignee: R3 Logic, Inc.
• Original Assignee: R3 Logic, Inc.
• Inventors: McIlrath, Lisa G.
• Primary Examiner(s): DOAN, NGHIA M
• Application Number:
  US12/537,500
• Publication Number:
  US 20100005437A1
• Time in Patent Office: 1,054 Days
• Field of Search: 716100-106, 716110-111, 716116-119, 716/122, 716/132, 716138-139, 716/126
• US Class Current: 716/110
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

Claims

1. A method for defining a 3-D technology file structure, the method comprising the steps of:

providing a first circuit level identifier for a first circuit level in a 3-D integrated circuit;

providing a second circuit level identifier for a second circuit level in said 3-D integrated circuit;

providing a first 2-D technology file identifier for a 2-D technology file containing technology dependent information corresponding to said first circuit level;

providing a second 2-D technology file identifier for a 2-D technology file containing technology dependent information corresponding to said second circuit level;

creating a file structure configured for use in generating a 3-D integrated circuit layout, said file structure comprising said first circuit level identifier, said first 2-D technology file identifier, said second circuit level identifier and said second 2-D technology file identifier; and

storing said file structure in a computer usable storage device.

2. The method of claim 1, further comprising:

said 2-D technology file identifier comprising a pointer to said 2-D technology file.

3. The method of claim 1 further comprising:

assigning a 2-D technology to each of said first circuit level and said second circuit level.

4. The method of claim 1, further comprising:

said 2-D technology file comprising a pre-existing 2-D technology file.

5. The method of claim 1, further comprising:

providing an identifier for a bond layer disposed between said first circuit level and said second circuit level.

6. The method of claim 5 further comprising:

providing a list comprising said first circuit level identifier, said second circuit level identifier and said identifier for said bond layer;

said first circuit level identifier, said second circuit level identifier and said identifier for said bond layer being located in an order in which said first circuit level, said second circuit level and said bond layer are located in said 3-D integrated circuit.

7. The method of claim 6, further comprising:

accessing said technology file structure by executing computer readable code on at least one processor.

8. The method of claim 7, further comprising:

generating a 3-D integrated circuit layout for said 3-D integrated circuit in accordance with said 3-D technology file structure.

9. The method of claim 7, further comprising:

verifying a 3-D integrated circuit layout for said 3-D integrated circuit in accordance with said 3-D technology file structure.

10. The method of claim 1, further wherein said file structure is configured for use in verifying said 3-D integrated circuit layout.

11. A system for defining a 3-D technology file structure, comprising:

at least one processor;

at least one computer usable storage device, accessible by said at least one processor; and

a data structure stored on said at least one computer usable storage device, said data structure configured for use in generating a 3-D integrated circuit layout, said data structure including a circuit level identifier for each of at least two circuit levels in a 3-D integrated circuit, and a technology file identifier for each of said at least two circuit levels, each of said technology file identifiers identifying a 2-D technology file containing technology dependent information for a corresponding one of said at least two circuit levels.

12. The system of claim 11, further comprising:

said identifier for the 2-D technology file comprising a pointer to the 2-D technology file.

13. The system of claim 11 further comprising:

computer readable code executable by said at least one processor to assign a 2-D technology to each of said at least two circuit levels.

14. The system of claim 11, wherein said 2-D technology file comprises a pre-existing 2-D technology file.

15. The system of claim 11, wherein said data structure further comprises an identifier for a bond layer disposed between said at least two circuit levels.

16. The system of claim 15 further wherein said data structure further includes a list comprising said first circuit level identifier for each of said at least two circuit levels in said 3-D integrated circuit and said identifier for said bond layer in an order in which said circuit level identifier for each of said at least two circuit levels in said 3-D integrated circuit and said bond layer are located in said 3-D integrated circuit.

17. The method of claim 11, further wherein said data structure is configured for use in verifying said 3-D integrated circuit layout.

18. A method for defining a 3-D technology file structure, the method comprising the steps of:

providing a circuit level identifier for each of at least two circuit levels in a 3-D integrated circuit;

providing for each one of said at least two circuit levels, a 2-D technology file identifier for a 2-D technology file containing technology dependent information corresponding to said one of said at least two circuit levels;

creating a file structure configured for use in generating a 3-D integrated circuit layout, said file structure comprising said circuit level identifier for each of said at least two circuit levels and said 2-D technology file identifier for the 2-D technology file corresponding to said each one of said at least two circuit levels; and

storing said file structure in a computer usable storage device.

19. The method of claim 18, further comprising:

said 2-D technology file identifier comprising a pointer to the 2-D technology file.

20. The method of claim 18 further comprising:

assigning a 2-D technology to each of said at least two circuit levels.

21. The method of claim 18, further comprising:

said 2-D technology file selected from the group consisting of a pre-existing 2-D technology file and a user generated 2-D technology file.

22. The method of claim 18, further comprising:

providing an identifier for a bond layer disposed between said at least two circuit levels; and

providing a list comprising said circuit level identifier for each said at least two circuit levels and said identifier for said bond layer;

said circuit level identifier for each said at least two circuit levels and said identifier for said bond layer being located in an order in which said at least two circuit levels and said bond layer are located in said 3-D device integrated circuit.

23. The method of claim 18, further wherein said file structure is configured for use in verifying said 3-D integrated circuit layout.