Structure having silicon CMOS transistors with column III-V transistors on a common substrate

• US 8,212,294 B2
• Filed: 01/28/2010
• Issued: 07/03/2012
• Est. Priority Date: 01/28/2010
• Status: Active Grant

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Hoke, William E., LaRoche, Jeffrey R.
• Primary Examiner(s): Tran, Tan N
• Application Number:
  US12/695,518
• Publication Number:
  US 20110180857A1
• Time in Patent Office: 887 Days
• Field of Search: 257/255, 257/627, 257/369, 257/E27.062
• US Class Current: 257/255
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence

Abstract

A semiconductor structure having: a silicon substrate having a crystallographic orientation; an insulating layer disposed over the silicon substrate; a silicon layer having a different crystallographic orientation than the crystallographic orientation of the substrate disposed over the insulating layer; and a column III-V transistor device having the same crystallographic orientation as the substrate disposed on the silicon substrate. In one embodiment, the column III-V transistor device is in contact with the substrate. In one embodiment, the device is a GaN device. In one embodiment, the crystallographic orientation of the substrate is <111> and wherein the crystallographic orientation of the silicon layer is <100>. In one embodiment, CMOS transistors are disposed in the silicon layer. In one embodiment, the column III-V transistor device is a column III-N device. In one embodiment, a column III-As, III-P, or III-Sb device is disposed on the top of the <100> silicon layer.

Claims

1. A semiconductor structure comprising:

a silicon substrate having a <

111>

crystallographic orientation;

an insulating layer disposed over a first portion of the silicon substrate;

a silicon layer disposed over the insulating layer;

wherein the silicon layer has a <

100>

orientation which is a different crystallographic orientation than the crystallographic orientation of the substrate; and

a column III-V device having the same crystallographic orientation as the substrate disposed on a second portion of the silicon substrate.

2. The structure recited in claim 1 wherein the column III-V device is in contact with the substrate.

3. The structure recited in claim 2 wherein the column III-V device is a column III-N device.

4. The structure recited in claim 3 including CMOS transistors disposed in the silicon layer.

5. The structure recited in claim 2 including CMOS transistors disposed in the silicon layer.

6. The semiconductor structure recited in claim 2 including a column III-As, column III-P, or column III-Sb device on the silicon layer.

7. The semiconductor structure recited in claim 3 including a column III-As, column III-P, or column III-Sb device on the silicon layer.

8. The semiconductor structure recited in claim 1 including a column III-As, column III-P, or column III-Sb device on the silicon layer.