Shared bit line and source line resistive sense memory structure

• US 8,213,216 B2
• Filed: 04/14/2011
• Issued: 07/03/2012
• Est. Priority Date: 07/13/2009
• Status: Active Grant

• Current Assignee: Everspin Technologies Incorporated
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Wang, Xuguang, Li, Hai, Liu, Hongyue
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US13/086,869
• Publication Number:
  US 20110188301A1
• Time in Patent Office: 446 Days
• Field of Search: 365/148, 365/100, 365/173, 365/145, 365/158, 365/196
• US Class Current: 365/148
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A resistive sense memory apparatus includes a first semiconductor transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first resistive sense memory element and a second semiconductor transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second resistive sense memory element. A bit line is electrically connected to the first resistive sense memory element and the second resistive sense memory element.

Claims

1. A spin transfer torque memory apparatus comprising:

a first transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first spin transfer torque memory element;

a second transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second spin transfer torque memory element; and

a bit line electrically connected to the first spin transfer torque memory element and the second spin transfer torque memory element at the same location on the bit line.

2. The spin transfer torque memory apparatus according to claim 1, wherein the first transistor and the second transistor adjacent to each other and electrically isolated from each other.

3. The spin transfer torque memory apparatus according to claim 1, further comprising a third transistor adjacent to the first transistor, the third transistor sharing the first contact electrically connected to the first source line, the third transistor having a second contact electrically connected to a third spin transfer torque memory element.

4. The spin transfer torque memory apparatus according to claim 3, wherein the third transistor and the first transistor have a common source contact region.

5. The spin transfer torque memory apparatus according to claim 1, further comprising a fourth transistor having a first contact electrically connected to a third source line and a second contact electrically connected to a fourth spin transfer torque memory element, a second bit line electrically connected to the third spin transfer torque memory element and the fourth spin transfer torque memory element.

6. The spin transfer torque memory apparatus according to claim 1, wherein the first transistor and second transistor are electrically connected to a common word line.

7. The spin transfer torque memory apparatus according to claim 1, wherein the first spin transfer torque memory element and the second spin transfer torque memory element are memory elements of a memory array.

8. The spin transfer torque memory apparatus according to claim 5, wherein the first transistor, second transistor, third transistor, and fourth transistor are electrically connected to a common word line.

9. A spin transfer torque memory apparatus comprising:

a first transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first spin transfer torque memory element;

a second transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second spin transfer torque memory element;

a bit line electrically connected to the first spin transfer torque memory element and the second spin transfer torque memory element at the same location on the bit line; and

a third transistor sharing the first contact electrically connected to the first source line at the first contact location, the third transistor having a second contact electrically connected to a third spin transfer torque memory element, and the third resistive spin transfer torque element electrically connected to a second bit line.

10. The spin transfer torque memory apparatus according to claim 9, further comprising a fourth transistor having a first contact electrically connected to a third source line and a second contact electrically connected to a forth spin transfer torque memory element, the second bit line electrically connected to the third spin transfer torque memory element and the fourth spin transfer torque memory element.

11. The spin transfer torque memory apparatus according to claim 10, wherein the first transistor and the second transistor are adjacent to each other and electrically isolated from each other and the third transistor and the fourth transistor are adjacent to each other and electrically isolated from each other.

12. The spin transfer torque memory apparatus according to claim 9, wherein the first transistor and second transistor are electrically connected to a common word line.

13. The spin transfer torque memory apparatus according to claim 9, wherein the first spin transfer torque memory element and the second spin transfer torque memory element are memory elements of a memory array.

14. The spin transfer torque memory apparatus according to claim 10, wherein the first transistor, second transistor, third transistor, and fourth transistor are electrically connected to a common word line.

15. A method of accessing a spin transfer torque memory cell in a memory array comprising:

providing a spin transfer torque memory array comprising;

a first transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first spin transfer torque memory element;

a second transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second spin transfer torque memory element;

a bit line electrically connected to the first spin transfer torque memory element and the second spin transfer torque memory element at the same location on the bit line; and

a third transistor sharing the first contact electrically connected to the first source line at the first contact location, the third transistor having a second contact electrically connected to a third spin transfer torque memory element, and the third spin transfer torque memory element electrically connected to a second bit line;

applying a source voltage to the first source line and the second bit line;

applying a drain voltage to the first bit line and second source line; and

applying a gate voltage to the first transistor, second transistor and third transistor to flow current through the first spin transfer torque memory element.

16. The method according to claim 15, wherein the current is a read current.

17. The method according to claim 15, wherein the current is a write current.

18. The method according to claim 15, wherein source lines adjacent to the first source line and second source line are floating.

19. The method according to claim 15, wherein bit lines adjacent to the first bit line and second bit line are floating.

20. The method according to claim 15, wherein the first transistor, second transistor, third transistor are electrically connected to a common word line and the gate voltage is applied to the word line.