Method of partitioning an algorithm between hardware and software

• US 8,230,374 B2
• Filed: 12/14/2007
• Issued: 07/24/2012
• Est. Priority Date: 05/17/2002
• Status: Active Grant

• Current Assignee: Pixel Velocity Incorporated
• Original Assignee: Pixel Velocity Incorporated
• Inventors: McCubbrey, David L.
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US11/957,287
• Publication Number:
  US 20080148227A1
• Time in Patent Office: 1,684 Days
• Field of Search: 716/101, 716/105, 716/116
• US Class Current: 716/116
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 8/456 Parallelism detection
• CPC Class Codes: H05K 1/144 Stacked arrangements of planar printed circuit boards

Abstract

A method of partitioning an algorithm between hardware and software includes accepting a user defined algorithm specified in a source code, identifying worker methods and feature extraction methods within the user defined algorithm, replacing worker methods in the source code with hardware logic, replacing feature extraction methods with a combination of hardware logic and software libraries that interface with the hardware logic, and outputting an FPGA programming specification of the hardware logic and interface libraries.

Claims

1. A computer program product for partitioning an algorithm between hardware and software comprising:

a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising;

computer readable program code to accept a user defined algorithm specified in a source code;

computer readable program code to identify worker methods and feature extraction methods within the user defined algorithm, wherein the feature extraction methods comprise methods selected from the group consisting of;

generating histograms of image pixel values, listing image coordinate/value pairs, counting pixels having a specific value, listing features, listing feature locations, listing maximum and minimum values, listing minimum and maximum value locations;

computer readable program code to replace worker methods in the source code with hardware logic;

computer readable program code to replace feature extraction methods with a combination of hardware logic and software libraries that interface with the hardware logic;

computer readable program code to output an FPGA programming specification of the hardware logic and interface libraries; and

computer readable program code to program an FPGA in response to the FPGA programming specification.

2. The computer program product of claim 1, wherein the source code is specified in a high level programming language.

3. The computer program product of claim 1, wherein the source code is specified in C++.

4. The computer program product of claim 1, wherein the identifying step includes parsing the source code.

5. The computer program product of claim 1, wherein the worker methods are image processing methods.

6. The computer program product of claim 1, wherein the computer readable program code to replace worker methods comprises computer readable program code to stub out the source code that corresponds to the worker methods.

7. The computer program product of claim 1, wherein the feature extraction methods output symbolic information.

8. The computer program product of claim 1, wherein the interface libraries are real-time embedded libraries.

9. The computer program product of claim 8, wherein the real-time embedded libraries retrieve data from the hardware logic.

10. The computer program product of claim 9, wherein the input data set is collected under the same conditions as deployment.

11. The computer program product of claim 10, wherein the input data set is collected using an embedded target machine.

12. The computer program product of claim 1, further comprising computer readable program code to test the software program with an input data set.

13. The computer program product of claim 1, wherein the FPGA programming specification is in a vendor specific low-level format.

14. The computer program product of claim 1, wherein the FPGA programming specification is a hardware gate programming bitstream.

15. A computer implemented method of programming a field programmable gate array (FPGA) with an algorithm by partitioning the algorithm between hardware and software, the method comprising:

accepting a user defined algorithm specified in source code;

identifying, by an analyzer module, worker methods and feature extraction methods within the user defined algorithm;

replacing, by a mapper module, worker methods in the source code with hardware logic;

replacing, by the mapper module, feature extraction methods with a combination of hardware logic and software libraries that interface with the hardware logic, wherein the feature extraction methods comprise methods selected from the group consisting of;

generating histograms of image pixel values, listing image coordinate/value pairs, counting pixels having a specific value, listing features, listing feature locations, listing maximum and minimum values, listing minimum and maximum value locations;

generating a FPGA programming specification of the hardware logic and interface libraries; and

programming at least one target FPGA using the FPGA programming specification.

16. The method of claim 15, wherein hardware logic includes hardware component mappings and wherein the step of programming at least one target FPGA includes mapping the hardware components on the FPGA.