Layout generating method for semiconductor integrated circuits

• US 8,230,379 B2
• Filed: 10/18/2007
• Issued: 07/24/2012
• Est. Priority Date: 10/20/2006
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kobayashi, Sachiko, Kyoh, Suigen
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US11/874,601
• Publication Number:
  US 20080098341A1
• Time in Patent Office: 1,741 Days
• Field of Search: 716/126, 716/132, 716/136, 716/139
• US Class Current: 716/132
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A design layout generating method for generating a design pattern of a semiconductor integrated circuit is disclosed. This method comprises modifying a first modification area extracted from a design layout by a first modifying method, and modifying a second modification area extracted from the design layout so as to include the first modification area by a second modifying method on the basis of a pattern modifying guideline calculated from at least a partial design layout in the second modification area.

Claims

1. A design layout generating method, the method including:

modifying, using a computer, a first design pattern for a semiconductor device, included in a first modification area extracted from a design layout by a first modifying method; and

modifying, using the computer, a second design pattern for the semiconductor device, included in a second modification area extracted from the design layout by a second modifying method on the basis of a pattern modifying guideline calculated from at least a partial design layout in the second modification area, such that the second modification area includes the first modification area,

wherein, when two second modification areas extracted from a design layout are close to each other or parts of them overlap with each other, the two second modification areas are put together into a single second modification area.

2. The design layout generating method according to claim 1, wherein the pattern modifying guideline is calculated by a specified algorithm.

3. The design layout generating method according to claim 1, wherein the first modifying method is a method of making a modification by referring to a rule table in which a modifying guideline has been determined for design layouts.

4. The design layout generating method according to claim 1, wherein the second modifying method includes any one of a model-based modifying method, a group modifying method, a pattern matching modifying method, a jog division modifying method, a pattern interval easing modifying method, a modifying method involving increase and decrease of a number of layers to be moved, and a design-rule easing modifying method.

5. The design layout generating method according to claim 1, wherein, if the pattern formed on the wafer according to the design layout modified by the second modifying method does not satisfy a specified evaluated value, further modifying the design layout modified by the second modifying method.

6. The design layout generating method according to claim 5, wherein, when the design layout modified by the second modifying method is further modified, modifying the design layout on the basis of a pattern modifying guideline newly worked out referring to the pattern modifying guideline used in the second modification.

7. The design layout generating method according to claim 1, wherein the first modification area includes a design layout area where an evaluated value calculated on the basis of a pattern formed on the wafer according to the design layout does not satisfy a specified value in the design layout, and

the second modification area includes an area where an evaluated value calculated on the basis of a pattern formed on the wafer according to the design layout modified by the first modifying method does not satisfy a specified value in the design layout modified by the first modifying method.

8. The design layout generating method according to claim 7, wherein the evaluated value of the design layout is calculated on the basis of a process margin of the pattern formed on the wafer.

9. The design layout generating method according to claim 7, wherein the two or more second modification areas extracted from the design layout are modified in order of increasing the evaluated values of their design layouts located in the second area.

10. A design layout generating method, the method including:

modifying, using a computer, a first design pattern for a semiconductor device, included in a first modification area extracted from a design layout by a first modifying method; and

modifying, using the computer, a second design pattern for the semiconductor device, included in a second modification area extracted from the design layout by a second modifying method on the basis of a pattern modifying guideline calculated from at least a partial design layout in the second modification area, such that the second modification area includes the first modification area,

wherein the first and second modifying methods are so configured that an evaluated value calculated on the basis of a pattern formed on a wafer according to a design layout modified by the first modifying method is higher than an evaluated value calculated on the basis of a pattern formed on the wafer according to a design layout before modification by the first modifying method and that an evaluated value calculated on the basis of a pattern formed on the wafer according to a design layout modified by the second modifying method is higher than an evaluated value calculated on the basis of a pattern formed on the wafer according to a design layout before modification by the second modifying method.

11. A non-transitory computer-readable medium configured to store program instructions for execution on a computer, the program instructions causing the computer to perform:

modifying, using the computer, a first design pattern for a semiconductor, included in a first modification area extracted from a design layout by a first modifying method; and

modifying, using the computer, a second design pattern for the semiconductor device, included in a second modification area extracted from the design layout by a second modifying method on the basis of a pattern modifying guideline calculated from at least a partial design layout in the second modification area, such that the second modification area includes the first modification area,

wherein, when two second modification areas extracted from a design layout are close to each other or parts of them overlap with each other, the two second modification areas are put together into a single second modification area.

12. A non-transitory computer-readable medium configured to store program instructions for execution on a computer, the program instructions causing the computer to perform:

modifying, using the computer, a first design pattern for a semiconductor, included in a first modification area extracted from a design layout by a first modifying method; and

modifying, using the computer, a second design pattern for the semiconductor device, included in a second modification area extracted from the design layout by a second modifying method on the basis of a pattern modifying guideline calculated from at least a partial design layout in the second modification area, such that the second modification area includes the first modification area,

wherein the first and second modifying methods are so configured that an evaluated value calculated on the basis of a pattern formed on a wafer according to a design layout modified by the first modifying method is higher than an evaluated value calculated on the basis of a pattern formed on the wafer according to a design layout before modification by the first modifying method and that an evaluated value calculated on the basis of a pattern formed on the wafer according to a design layout modified by the second modifying method is higher than an evaluated value calculated on the basis of a pattern formed on the wafer according to a design layout before modification by the second modifying method.