Stacked-chip device

• US 8,232,622 B2
• Filed: 08/25/2009
• Issued: 07/31/2012
• Est. Priority Date: 08/26/2008
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Urakawa, Yukihiro
• Primary Examiner(s): Lee, Eugene
• Assistant Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US12/546,806
• Publication Number:
  US 20100052096A1
• Time in Patent Office: 1,071 Days
• Field of Search: 257/531, 257/686, 257/737, 438/109, 438/613
• US Class Current: 257/531
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 Diameter ranges

Abstract

A stacked-chip device includes a first inductive chip having a first function, a second inductive chip having a second function different from the first function, which is stacked on the first inductive chip, and a third inductive chip having the second function, which is stacked on the second inductive chip. Each of the first, second and third inductive chips has transmitting inductors which transmit data and receiving inductors which receive data. The transmitting inductors and the receiving inductors are disposed in line symmetry to an axis of symmetry. The axes of symmetry of the first, second and third inductive chips are overlapped. Each of the second and third inductive chips is disposed in upside-down or back to front to the first inductive chip.

Claims

1. A stacked-chip device comprising:

a first inductive chip having a first function;

a second inductive chip having a second function different from the first function, which is stacked on the first inductive chip; and

a third inductive chip having the second function, which is stacked on the second inductive chip,

wherein each of the first, second and third inductive chips has an array of transmitting inductors which transmit data and receiving inductors which receive data,

wherein an order of arranging the transmitting inductors and the receiving inductors is the same in the first, second and third inductive chips,

wherein the transmitting inductors and the receiving inductors in the first inductive chip are arranged symmetrically with respect to a first line, the transmitting inductors and the receiving inductors in the second inductive chip are arranged symmetrically with respect to a second line which passes through a center of the second inductive chip, and the transmitting inductors and the receiving inductors in the third inductive chip are arranged symmetrically with respect to a third line which passes through a center of the third inductive chip,

wherein the first, second and third lines are overlapped,

wherein the second inductive chip is disposed in upside-down or back to front to the first and third inductive chips.

2. The device according to claim 1,

wherein the first inductive chip is a control chip which controls the second and third inductive chips, and each of the second and third inductive chips is a memory chip.

3. The device according to claim 2,

wherein the number of the transmitting inductors is larger than that of the receiving inductors in the first inductive chip.

4. The device according to claim 2,

wherein the number of the receiving inductors is larger than that of the transmitting inductors in each of the second and third inductive chips.

5. The device according to claim 1,

wherein data is transferred by a bucket-brigade system in which data is transferred from the second inductive chip to the third inductive chip after transferred from the first inductive chip to the second inductive chip.

6. The device according to claim 1,

wherein data is transferred by a bucket-brigade system in which data is transferred from the second inductive chip to the first inductive chip after transferred from the third inductive chip to the second inductive chip.

7. The device according to claim 1, further comprising

a package board having first and second surfaces;

and

bumps which is provided on the first surface of the package board,

wherein the first, second and third inductive chips are provided on the second surface of the package board.

8. The device according to claim 1,

wherein layouts of the transmitting inductors and the receiving inductors of the first, second and third inductive chips are the same.