Dummy gate structure for gate last process

  • US 8,237,227 B2
  • Filed: 06/03/2009
  • Issued: 08/07/2012
  • Est. Priority Date: 08/29/2008
  • Status: Active Grant
First Claim
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1. A device, comprising:

  • a semiconductor substrate having a first portion, a second portion, and a third portion;

    a plurality of transistors formed in the first portion of the substrate, each transistor having a gate structure with a high-k dielectric and a metal gate;

    a first transistor having a metal gate structure formed in the second portion of the substrate, the first transistor being isolated by an isolation region; and

    a first polishing stopper formed adjacent the isolation region and having a surface that is substantially planar with a surface of the gate structures of the transistors in the first region, the first polishing stopper including a plurality of dummy structures configured in a ring formation formed in and around an edge of the second portion such that the plurality of dummy structures encircle the metal gate structure, source and drain region of the first transistor and wherein the first polishing stopper covers at least 5% of a pattern density of the second portion of the substrate;

    a fabrication device including at least one of a monitor pad and an alignment mark formed in the third portion, wherein the monitor pad includes a plurality of layers disposed in a stack including a high-k dielectric layer and a second layer formed on the high-k dielectric layer, wherein the second layer is a metal layer comprising the same metal as the metal gate of the plurality of transistors, and wherein the alignment mark is operable to be used to align a photomask and the semiconductor substrate during a photolithography process; and

    a second polishing stopper formed in the third portion adjacent the fabrication device, wherein the second polishing stopper includes a plurality of dummy structures disposed adjacent at least two sides of the fabrication device.

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