Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipation

• US 8,237,252 B2
• Filed: 07/22/2009
• Issued: 08/07/2012
• Est. Priority Date: 07/22/2009
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Pagaila, Reza A., Do, Byung Tai, Chua, Linda Pei Ee
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US12/507,130
• Publication Number:
  US 20110018114A1
• Time in Patent Office: 1,112 Days
• Field of Search: 257/712, 257/723, 257/686, 257/698, 257/706, 257/E21.597, 257/E21.506, 257/E21.505, 257/E23.141, 257/E23.011, 257/E23.101, 438/108, 438/117, 438/122, 438/124, 438/126, 438/127
• US Class Current: 257/686
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device is made by forming a first thermally conductive layer over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer.

Claims

1. A method of making a semiconductor device, comprising:

forming a first thermally conductive layer over a first surface of a semiconductor die;

providing a sacrificial carrier;

mounting a second surface of the semiconductor die, opposite the first surface of the semiconductor die, to the sacrificial carrier;

depositing an encapsulant over the first thermally conductive layer and sacrificial carrier;

planarizing the encapsulant to expose the first thermally conductive layer;

removing the sacrificial carrier;

forming a first insulating layer over the second surface of the semiconductor die and a first surface of the encapsulant;

removing a portion of the first insulating layer over the second surface of the semiconductor die;

forming a second thermally conductive layer over the second surface of the semiconductor die within the removed portion of the first insulating layer; and

forming an electrically conductive layer in the insulating layer around the second thermally conductive layer.

2. The method of claim 1, further including forming solder bumps over the electrically conductive layer and second thermally conductive layer.

3. The method of claim 1, further including forming a conductive through silicon via in the semiconductor die between the first and second thermally conductive layers.

4. The method of claim 1, further including:

forming a conductive bump over contact pads of the semiconductor die; and

forming a third thermally conductive layer between the second surface of the semiconductor die and the second thermally conductive layer.

5. The method of claim 1, further including:

forming an interconnect structure over the first thermally conductive layer and a second surface of the encapsulant;

forming a third thermally conductive layer within the interconnect structure; and

forming a conductive through hole via in the encapsulant between the interconnect structure and electrically conductive layer.

6. The method of claim 1, further including mounting a heat sink over the first surface of the encapsulant and first thermally conductive layer.

7. The method of claim 1, further including mounting first and second semiconductor die back-to-back mated by the first thermally conductive layers of the first and second semiconductor die.

8. A method of making a semiconductor device, comprising:

providing a sacrificial carrier;

mounting a semiconductor component to the sacrificial carrier, the semiconductor component having a first thermally conductive layer formed over a surface of the semiconductor component;

depositing an encapsulant over the semiconductor component and sacrificial carrier;

removing the sacrificial carrier;

forming a first interconnect structure over the semiconductor component and a first surface of the encapsulant; and

forming a second thermally conductive layer within the first interconnect structure, the first and second thermally conductive layers providing heat dissipation from the semiconductor component.

9. The method of claim 8, further including planarizing the encapsulant to expose the first thermally conductive layer.

10. The method of claim 8, further including forming a conductive through silicon via in the semiconductor component between the first and second thermally conductive layers.

11. The method of claim 8, further including:

forming a conductive bump over contact pads of the semiconductor component; and

forming a third thermally conductive layer between the semiconductor component and second thermally conductive layer.

12. The method of claim 8, further including mounting a heat sink over the first surface of the encapsulant and first thermally conductive layer.

13. The method of claim 8, further including mounting first and second semiconductor components back-to-back mated by the first thermally conductive layers of the first and second semiconductor component.

14. A method of making a semiconductor device, comprising:

providing a semiconductor component with a first thermally conductive layer formed over a surface of the semiconductor component;

depositing an encapsulant over the semiconductor component;

forming a first interconnect structure over the semiconductor component and a first surface of the encapsulant; and

forming a second thermally conductive layer within the first interconnect structure, the first and second thermally conductive layers providing heat dissipation from the semiconductor component.

15. The method of claim 14, further including planarizing the encapsulant to expose the first thermally conductive layer.

16. The method of claim 14, further including forming a conductive through silicon via in the semiconductor component between the first and second thermally conductive layers.

17. The method of claim 14, further including:

forming a conductive bump over contact pads of the semiconductor component; and

forming a third thermally conductive layer between the semiconductor component and second thermally conductive layer.

18. The method of claim 14, further including mounting a heat sink over the first surface of the encapsulant and first thermally conductive layer.

19. The method of claim 14, further including mounting first and second semiconductor components back-to-back mated by the first thermally conductive layers of the first and second semiconductor components.