On-chip service processor

• US 8,239,716 B2
• Filed: 03/04/2010
• Issued: 08/07/2012
• Est. Priority Date: 03/25/1998
• Status: Expired due to Fees

• Current Assignee: American Patents LLC
• Original Assignee: Intellectual Ventures I LLC (Intellectual Ventures LLC)
• Inventors: Dervisoglu, Bulent I., Cooke, Laurence H., Arat, Vacit
• Primary Examiner(s): Ton, David
• Application Number:
  US12/717,391
• Publication Number:
  US 20100162046A1
• Time in Patent Office: 887 Days
• Field of Search: 714/30, 714/39, 714/733, 714/726, 714/727, 714/729, 714/734, 714/32, 703/28
• US Class Current: 714/726
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test
• CPC Class Codes: G01R 31/318572 Input/Output interfaces

Abstract

An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

Claims

1. An integrated circuit comprising:

one or more logic blocks configured to generate one or more system operation signals at one or more system operation clock rates;

a service processor unit configured to perform one or more debug operations on one or more of said logic blocks, the service processor unit comprising;

a control unit,

a buffer memory,

an analysis engine, and

a bus interface; and

a multiplicity of probe lines configured to capture and propagate one or more of said one or more system operation signals from said logic blocks to said service processor unit during normal system operation;

wherein said analysis engine is configured to align signals received from said probe lines during normal system operation.

2. The integrated circuit as in claim 1, wherein said analysis engine includes a variable first-in, first-out (FIFO) element.

3. The integrated circuit as in claim 1, wherein said analysis engine is configured to store aligned signals in said buffer memory.