Method and apparatus for tuning phase of clock signal

• US 8,242,819 B2
• Filed: 03/07/2011
• Issued: 08/14/2012
• Est. Priority Date: 04/08/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Bae, Seung Jun, Park, Kwang Il, Bang, Sam Young, Moon, Gil Shin, Yeom, Ki Woong
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US13/042,244
• Publication Number:
  US 20110158030A1
• Time in Patent Office: 526 Days
• Field of Search: 327/147, 327/156, 365/194
• US Class Current: 327/156
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop

Abstract

A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result.

Claims

1. A semiconductor memory apparatus configured to employ a data clock signal that has a different frequency than a main clock signal, the semiconductor memory apparatus comprising:

a clock signal receiver configured to receive the main clock signal and the data clock signal; and

a phase tuner configured to;

generate a frequency-divided clock signal having a same frequency as the main clock signal by dividing a frequency of the data clock signal,

generate from the frequency-divided clock signal at least four multiphase frequency-divided clock signals having the same frequency as the frequency-divided clock signal and different phases from one another,

compare each phase of the at least four multiphase frequency-divided clock signals with a phase of the main clock signal, and output a phase detection signal, and

compare a phase of a signal selected, based on the phase detection signal, from the at least four multiphase frequency-divided clock signals with the phase of the main clock signal and output a comparison result.

2. The semiconductor memory apparatus as claimed in claim 1, wherein the phase tuner comprises:

a divider configured to divide a frequency of the data clock signal to generate the frequency-divided clock signal;

a multiphase signal generator configured to repeatedly shift the frequency-divided clock signal to generate the at least four multiphase frequency-divided clock signals at a predetermined phase interval and output the at least four multiphase frequency-divided clock signals; and

a phase detector configured to compare a phase of one of the at least four arranged multiphase frequency-divided clock signals with the phase of the main clock signal and generate the phase detection signal,

wherein the at least four arranged multiphase frequency-divided clock signals are used to transmit and receive data.

3. The semiconductor memory apparatus as claimed in claim 2, wherein the predetermined phase interval is 90 degrees and the at least four multiphase frequency-divided clock signals are signals obtained by shifting the frequency-divided clock signal by 0, 90, 180 and 270 degrees, respectively.

4. The semiconductor memory apparatus as claimed in claim 3, wherein the phase shift control signal is set in a mode register set circuit included in the semiconductor memory apparatus.

5. The semiconductor memory apparatus as claimed in claim 1, wherein the phase tuner comprises:

a divider configured to divide a frequency of the data clock signal so as to generate the frequency-divided clock signal;

a multiphase signal generator configured to shift the frequency-divided clock signal by a phase shift amount corresponding to a phase shift control signal set by a memory controller to generate a phase-shifted frequency-divided clock signal; and

a phase detector configured to compare a phase of the phase-shifted frequency-divided clock signal with the phase of the main clock signal and feed back a comparison result.

6. The semiconductor memory apparatus as claimed in claim 5, wherein the phase shift amount is 90 degrees, and

wherein the multiphase signal generator comprises:

a multiphase generator configured to repeatedly shift the frequency-divided clock signal by 90 degrees to generate 0, 90, 180 and 270 degree frequency-divided clock signals; and

a selector configured to arrange the 0, 90, 180 and 270 degree frequency-divided clock signals and output them in arranged order as first, second, third and fourth frequency-divided clock signals in response to the phase shift control signal.

7. The semiconductor memory apparatus as claimed in claim 6, wherein the phase shift control signal is set by the memory controller in a mode register set circuit included in the semiconductor memory apparatus.

8. The semiconductor memory apparatus as claimed in claim 1, wherein the frequency of the main clock signal is ½

of the frequency of the data clock signal and the phase tuner includes a divider configured to divide a frequency of the data clock signal by 2 to generate the frequency-divided clock signal.

9. The semiconductor memory apparatus as claimed in claim 1, wherein the comparison result is fed back to memory controller via a line used to transmit an error detection code to a memory controller.

10. The semiconductor memory apparatus as claimed in claim 1, wherein the signal selected from the at least four multiphase frequency-divided clock signals is one of two signals having their first edges closest to a first edge of the main clock signal among the at least four multiphase frequency-divided clock signals.

11. A memory controller for controlling at least one memory apparatus, the memory controller comprising:

a clock signal generator configured to generate a main clock signal having a predetermined frequency and a data clock signal having a frequency different from the predetermined frequency of the main clock signal;

a clock transmitter configured to transmit the main clock signal and the data clock signal to a first memory apparatus;

a command/address transmitter configured to transmit a command and an address to the first memory apparatus in response to the main clock signal; and

a data transceiver configured to transmit and receive data in response to the data clock signal,

wherein the memory controller adjusts a phase of the data clock signal by a predetermined phase step based on a comparison result fed back from the first memory apparatus and transmits a phase-adjusted data clock signal to the first memory apparatus, and

wherein the comparison result is signal generated by comparing a first frequency-divided clock signal, which is generated by dividing a frequency of the data clock signal with the main clock signal.

12. The memory controller as claimed in claim 11, wherein the memory controller sequentially changes a first phase shift control signal to sequentially shift the first frequency-divided clock signal by 0, 90, 180, and 270 degrees,

wherein the memory controller receives a phase detection signal corresponding to the comparison result from the first memory apparatus, which generates a frequency-divided clock signal by shifting the first frequency-divided clock signal by a phase shift amount corresponding to the first phase shift control signal when the first phase shift control signal changes, compares a phase of the generated frequency-divided clock signal with the phase of the main clock signal, and generates the phase detection signal, and

wherein the memory controller determines the first phase shift control signal for selecting a phase shift amount, by which the first frequency-divided clock signal is shifted, based on phase detection signals respectively generated with respect to the 0, 90, 180, and 270 degree shifts.

13. The memory controller as claimed in claim 12, wherein the memory controller determines the first phase shift control signal for selecting a signal having a phase difference of ±

45 degrees or less from the phase of the main clock signal from among frequency-divided clock signals generated by shifting the first frequency-divided clock signal by 0, 90, 180, and 270 degrees.

14. The memory controller as claimed in claim 12, wherein:

the memory controller further receives a second comparison result fed back from a second memory apparatus,

each of the main clock signal and the data clock signal is transmitted via a single common signal line and then distributed to each of the first and second memory apparatuses, and

the comparison result is a signal generated by comparing a second frequency-divided clock signal, which is generated by dividing a frequency of the data clock signal, with the main clock signal by the second memory apparatus.

15. The memory controller as claimed in claim 14, wherein:

the memory controller is configured to sequentially change a second phase shift control signal to sequentially shift the second frequency-divided clock signal by 0, 90, 180, and 270 degrees,

to receive a second phase detection signal corresponding to the second comparison result from the second memory apparatus,

to generate a frequency-divided clock signal by shifting the second frequency-divided clock signal by a phase shift amount corresponding to the second phase shift control signal when the second phase shift control signal changes,

to compare a phase of the generated frequency-divided clock signal with the phase of the main clock signal,

to generate the second phase detection signal,

to determine the second phase shift control signal for selecting a phase shift amount, by which the second frequency-divided clock signal is shifted, based on phase detection signals respectively generated and fed back from the second memory apparatus with respect to the 0, 90, 180, and 270 degree shifts.

16. The memory controller as claimed in claim 15, wherein the memory controller readjusts the phase of the data clock signal to an average of the phase of the data clock signal adjusted with respect to the first memory apparatus and the phase of the data clock signal adjusted with respect to the second memory apparatus and transmits a phase-readjusted data clock signal to the first memory apparatus and the second memory apparatus.