Non-volatile memory and method with write cache partition management methods

• US 8,244,960 B2
• Filed: 01/05/2009
• Issued: 08/14/2012
• Est. Priority Date: 01/05/2009
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Paley, Alexander, Gorobets, Sergey Anatolievich, Zilberman, Eugene, Bennett, Alan David, Traister, Shai, Tomlin, Andrew, Wu, William S., So, Bum Suck
• Primary Examiner(s): Dudek, Jr., Edward
• Assistant Examiner(s): VERDERAMO III, RALPH
• Application Number:
  US12/348,899
• Publication Number:
  US 20100174847A1
• Time in Patent Office: 1,317 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/224 Disk storage
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation

Abstract

A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. The cache memory has a capacity dynamically increased by allocation of blocks from the main memory in response to a demand to increase the capacity. Preferably, a block with an endurance count higher than average is allocated. The logical addresses of data are partitioned into zones to limit the size of the indices for the cache.

Claims

1. A nonvolatile memory, comprising:

an array of memory cells organized into a plurality of blocks, each block being a plurality of memory cells that are erasable together;

said array being partitioned into a first group of blocks and a second group of blocks;

a group of read/write circuits for reading or programming in the memory array a corresponding page of memory cells in parallel;

said first group of blocks having first-group pages that are each once programmable in between erasure, and the memory cells in the first-group page each storing one or more bit of data;

said second group of blocks having second-group pages that are each multi-time programmable with a partial page being once programmable each time, and the memory cells in the second-group page each storing one bit of data;

said second group of blocks having a capacity dynamically increased by allocation of blocks from said first group to said second group in response to a demand to increase the capacity;

a time stamp stored with each block, said time stamp having a value that is toggled when the block was programmed;

a free block list updated at predefined time intervals for listing blocks free for allocation and the time stamps of the blocks listed, such that a comparison between the time stamps of the block stored in the block and the free block list will indicate whether the block has old data or just been written with new data.

2. The nonvolatile memory as in claim 1, wherein:

a hot count is used to track the endurance history of each block in the first group; and

the blocks being allocated from said first group to said second group have higher hot counts than the average block of said first group.

3. The nonvolatile memory as in claim 1, wherein:

the data is addressable by assigned logical addresses;

a set of zones each defining an non-overlapping range of logical addresses; and

a set of indices for each zone to track the data stored in said second group with logical addresses of the zone.

4. The nonvolatile memory as in claim 3, wherein:

said set of zones contains one zone.

5. The nonvolatile memory as in claim 3, wherein:

said set of zones contains more than one zone.

6. The nonvolatile memory as in claim 3, wherein:

said set of zones are each partitioned in a predefined range logical addresses such that each corresponding set of indices does not exceed a predetermined size.

7. In a nonvolatile memory having an array of memory cells organized into a plurality of blocks, each block being a plurality of memory cells that are erasable together;

a method of operating the nonvolatile memory, comprising;

partitioning the array into a first group of blocks and a second group of blocks;

providing a group of read/write circuits for reading or programming in the memory array a corresponding page of memory cells in parallel;

said first group of blocks having first-group pages that are each once programmable in between erasure, and the memory cells in the first-group page each storing one or more bit of data;

said second group of blocks having second-group pages that are each multi-time programmable with a partial page being once programmable each time, and the memory cells in the second-group page each storing one bit of data; and

dynamically adjusting the capacity of the second group by allocating blocks from said first group to said second group in response to a demand to increase the capacity;

storing a time stamp with each block, the time stamp having a value that is toggled when the block was programmed;

updating a free block list at predefined time intervals for listing blocks free for allocation and the time stamps of the blocks listed, such that a comparison between the time stamps of the block stored in the block and the free block list will indicate whether the block has old data or just been written with new data.

8. The method as in claim 7, wherein:

a hot count is used to track the endurance history of each block in the first group; and

the blocks being allocated from said first group to said second group have higher hot counts than the average block of said first group.

9. The method as in claim 7, wherein:

the data is addressable by assigned logical addresses;

a set of zones each defining an non-overlapping range of logical addresses; and

a set of indices for each zone to track the data stored in said second group with logical addresses of the zone.

10. The method as in claim 9, wherein:

said set of zones contains one zone.

11. The method as in claim 9, wherein:

said set of zones contains more than one zone.

12. The method as in claim 9, wherein:

said set of zones are each partitioned in a predefined range logical addresses such that each corresponding set of indices does not exceed a predetermined size.