Sub-beam forming receiver circuitry for ultrasound system
First Claim
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1. An apparatus including multi-channel receiver circuitry for a sub-beam forming receiver of an ultrasound system, comprising:
- input signal delay circuitry responsive to one or more clock signals and each one of a plurality of incoming digital data signals by providing a respective plurality of delayed digital data signals, wherein each one of said plurality of incoming digital data signals has a first resolution and a first frequency;
signal selection circuitry coupled to said input signal delay circuitry and responsive to a first plurality of control data by selecting among each said respective plurality of delayed digital data signals to provide a plurality of selected delayed digital data signals;
output signal delay circuitry coupled to said signal selection circuitry and responsive to a second plurality of control data by delaying each of said plurality of selected delayed digital data signals to provide a plurality of further delayed digital data, wherein each one of said plurality of further delayed digital data signals has a second resolution and a second frequency, said second resolution is higher than said first resolution and said second frequency is lower than said first frequency of a corresponding one of said one of a plurality of incoming digital data signals; and
signal combining circuitry coupled to said output signal delay circuitry and responsive to said plurality of further delayed digital data signals by combining said plurality of further delayed digital data signals to provide a corresponding output data signal.
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Abstract
Multi-channel receiver circuitry for a sub-beam forming receiver of an ultrasound system in which digital filtering, down-sampling and successive data storage circuitry impose programmable fine and coarse time delays on received digital data signals.
24 Citations
11 Claims
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1. An apparatus including multi-channel receiver circuitry for a sub-beam forming receiver of an ultrasound system, comprising:
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input signal delay circuitry responsive to one or more clock signals and each one of a plurality of incoming digital data signals by providing a respective plurality of delayed digital data signals, wherein each one of said plurality of incoming digital data signals has a first resolution and a first frequency; signal selection circuitry coupled to said input signal delay circuitry and responsive to a first plurality of control data by selecting among each said respective plurality of delayed digital data signals to provide a plurality of selected delayed digital data signals; output signal delay circuitry coupled to said signal selection circuitry and responsive to a second plurality of control data by delaying each of said plurality of selected delayed digital data signals to provide a plurality of further delayed digital data, wherein each one of said plurality of further delayed digital data signals has a second resolution and a second frequency, said second resolution is higher than said first resolution and said second frequency is lower than said first frequency of a corresponding one of said one of a plurality of incoming digital data signals; and signal combining circuitry coupled to said output signal delay circuitry and responsive to said plurality of further delayed digital data signals by combining said plurality of further delayed digital data signals to provide a corresponding output data signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus including multi-channel receiver circuitry for a sub-beam forming receiver of an ultrasound system, comprising:
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input signal delay means for receiving one or more clock signals and each one of a plurality of incoming digital data signals and in response thereto providing a respective plurality of delayed digital data signals, wherein each one of said plurality of incoming digital data signals has a first resolution and a first frequency; signal selector means for receiving a first plurality of control data and in response thereto selecting among each said respective plurality of delayed digital data signals to provide a plurality of selected delayed digital data signals; output signal delay means for receiving a second plurality of control data and in response thereto delaying each of said plurality of selected delayed digital data signals to provide a plurality of further delayed digital data, wherein each one of said plurality of further delayed digital data signals has a second resolution and a second frequency, said second resolution is higher than said first resolution and said second frequency is lower than said first frequency of a corresponding one of said one of a plurality of incoming digital data signals; and signal combiner means for combining said plurality of further delayed digital data signals to provide a corresponding output data signal.
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Specification