Method and system for managing cache injection in a multiprocessor system
First Claim
1. A method for performing a direct memory access (DMA) transfer within a processing system including multiple processors, said method comprising:
- initiating said DMA transfer to a DMA transfer target memory image within a DMA transfer target memory over a bus;
determining in a cache controller managing a cache memory associated with a particular one of said multiple processors that said DMA transfer is occurring on said bus;
responsive to determining that said DMA transfer is occurring, copying data being transferred in said DMA transfer to a cache line in said cache memory during said DMA transfer; and
targeting said particular processor for executing a routine that accesses memory addresses of said DMA transfer target memory image, whereby said particular processor processes data transferred by said DMA transfer, wherein said targeting comprises identifying said particular processor subsequent to completion of said DMA transfer, and further comprising queuing said routine for execution by said particular processor.
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Accused Products
Abstract
A method and apparatus for managing cache injection in a multiprocessor system reduces processing time associated with direct memory access transfers in a symmetrical multiprocessor (SMP) or a non-uniform memory access (NUMA) multiprocessor environment. The method and apparatus either detect the target processor for DMA completion or direct processing of DMA completion to a particular processor, thereby enabling cache injection to a cache that is coupled with processor that executes the DMA completion routine processing the data injected into the cache. The target processor may be identified by determining the processor handling the interrupt that occurs on completion of the DMA transfer. Alternatively or in conjunction with target processor identification, an interrupt handler may queue a deferred procedure call to the target processor to process the transferred data. In NUMA multiprocessor systems, the completing processor/target memory is chosen for accessibility of the target memory to the processor and associated cache.
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Citations
27 Claims
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1. A method for performing a direct memory access (DMA) transfer within a processing system including multiple processors, said method comprising:
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initiating said DMA transfer to a DMA transfer target memory image within a DMA transfer target memory over a bus; determining in a cache controller managing a cache memory associated with a particular one of said multiple processors that said DMA transfer is occurring on said bus; responsive to determining that said DMA transfer is occurring, copying data being transferred in said DMA transfer to a cache line in said cache memory during said DMA transfer; and targeting said particular processor for executing a routine that accesses memory addresses of said DMA transfer target memory image, whereby said particular processor processes data transferred by said DMA transfer, wherein said targeting comprises identifying said particular processor subsequent to completion of said DMA transfer, and further comprising queuing said routine for execution by said particular processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A multiprocessor system, comprising:
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a plurality of processors each coupled to an associated one of a plurality of cache memories; at least one cache controller coupled to said associated cache memories, said at least one cache controller including a bus snooper for observing transfers on at least one bus coupling said cache memories to a memory and a transfer circuit for transferring data to cache lines managed by said cache controller in response to detecting that a direct memory access (DMA) transfer is taking place to said memory; and an executive program resident in a memory coupled to an executive processor of said multiprocessor system, comprising program instructions that initiate said DMA transfer to said memory, and program instructions that direct execution of a routine that accesses said data transferred to said cache lines by a particular processor associated with a particular cache containing said cache lines, wherein said executive program further comprises program instructions that identify said particular processor subsequent to completion of said DMA transfer, and program instructions that queue said routine for execution by said particular processor. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A computer program product comprising computer-readable storage media encoding program instructions forming part of an executive program for execution by a processor within a multiprocessor system, said multiprocessor system including a cache controller with a cache injection feature that loads values into a cache memory during a direct memory access (DMA) transfer to a memory within said multiprocessor system, said values being at least a portion of data transferred by said DMA transfer, and said program instructions comprising program instructions that:
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initiate said DMA transfer; and direct execution of a routine that accesses said values to a particular processor associated with said cache memory, whereby said particular processor processes said values, wherein said program instructions further comprise program instructions that;
identify said particular processor subsequent to completion of said DMA transfer; and
queue said routine for execution by said particular processor. - View Dependent Claims (22, 23, 24, 25, 26)
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27. A method for performing a direct memory access (DMA) transfer within a processing system including multiple processors, the method comprising:
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specifying a particular cache memory and an associated particular processor for handling data received from the DMA transfer using an affinity map that indicates latency relationships between a DMA transfer target memory and the multiple processors; initiating the DMA transfer to a DMA transfer target memory image within the DMA transfer target memory over a bus using a bus protocol containing an indication of the particular cache memory and particular processor; first determining in a cache controller managing a particular cache memory associated with a particular one of the multiple processors that the DMA transfer is occurring on the bus; second determining from the bus protocol of the DMA transfer that the particular cache memory and the particular processor are specified by the bus protocol to handle the data received from the DMA transfer; responsive to determining that the DMA transfer is occurring and that the particular cache memory is specified by the bus protocol, copying data being transferred in said DMA transfer to a cache line in said particular cache memory during said DMA transfer; receiving an interrupt indicating completion of the DMA transfer; executing an interrupt routine on one of the multiple processors other than the particular processor to handle the interrupt and schedule a deferred procedure call targeting said particular processor for execution; and executing the deferred procedure call on the particular processor to access memory addresses of the DMA transfer target memory image, whereby the particular processor processes data transferred by said DMA transfer.
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Specification