Self power down integrated circuit

• US 8,261,101 B1
• Filed: 03/31/2008
• Issued: 09/04/2012
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Wijaya, Honggo, Crotty, Patrick J.
• Primary Examiner(s): Elamin, M
• Application Number:
  US12/059,675
• Time in Patent Office: 1,618 Days
• Field of Search: 713/300, 713/310, 713320-324, 713/330, 713/340, 326/38, 326/39, 326/41
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A suspend mode is provided that can be asserted using an Internal Configuration Access Port (ICAP) of an integrated circuit such as a Field Programmable Gate Array (FPGA), as supposed to a dedicated external suspend pin typically accessed by a device external to the FPGA. The ICAP is designed to assert the suspend mode through a configuration block to maintain the state of the configuration memory array while lowering power, in a similar manner to when an external suspend pin is accessed. Internal circuits can, thus, be used to assert a suspend mode through the ICAP.

Claims

1. A method for providing a suspend mode in an integrated circuit (IC) comprising:

providing a suspend instruction to an internal configuration access port (ICAP) of the IC, wherein the ICAP provides access to a configuration block to enable writing data in a configuration memory;

decoding the suspend instruction in the configuration block;

preserving a configuration memory state of the IC after decode of the suspend instruction to prepare for a low power mode;

preserving an internal register state of the IC after decode of the suspend instruction to prepare for a low power mode;

entering the low power mode after decode of the suspend instruction, wherein the ICAP is powered down in the low power mode;

providing a wakeup signal to the configuration block of the IC; and

entering a high power mode in response to the wakeup signal while maintaining the configuration memory state and the internal register state of the IC.

2. The method of claim 1, wherein the suspend instruction is generated by a watchdog timer having a programmable time period, wherein the suspend instruction is provided when the IC does not change states for the programmable time period.

3. The method of claim 1, wherein the suspend instruction is provided by circuitry forming a module provided in the IC.

4. The method of claim 1, wherein the suspend instruction can be provided from a plurality of signal pins of the IC.

5. The method of claim 1, wherein the suspend mode is decoded by a state machine of the configuration block, and wherein the configuration block controls configuration circuitry to maintain the state of the configuration memory.

6. A method for providing a suspend mode in an integrated circuit (IC) comprising:

providing a suspend mode interrupt signal to an internal configuration access port (ICAP) of the IC, wherein the ICAP provides access to a configuration block to enable writing data in a configuration memory;

identifying the suspend mode interrupt signal in the configuration block;

maintaining a configuration memory state and an internal register state of the IC using the configuration block after identification of the interrupt signal, while entering a low power mode, wherein the ICAP is powered down in the low power mode;

providing a wakeup signal to the configuration block of the IC; and

entering a high power mode in response to the wakeup signal while maintaining the configuration memory state and the internal register state of the IC.

7. The method of claim 6, wherein the suspend mode interrupt signal is provided by circuitry forming a module provided in the IC.

8. The method of claim 6, wherein the suspend mode interrupt signal is provided from a plurality of signal pins of the IC.

9. An integrated circuit (IC) comprising:

a configuration memory array;

configuration circuitry for programming of the configuration memory array;

a configuration block including a state machine to control configuring of the configuration memory array using the configuration circuitry, the state machine adapted to process a suspend instruction to cause the state of the configuration memory array to be maintained and then cause the IC to enter a low power mode; and

an internal configuration access port (ICAP) provided internal to the IC for providing the suspend mode instruction to the configuration block;

wherein the ICAP is powered down in the low power mode; and

wherein the state machine of the configuration block is further adapted to process a wakeup instruction to cause the IC to enter a high power mode while preserving the state of the configuration memory array.

10. The IC of claim 9, wherein the port comprises an internal configuration access port (ICAP).

11. The IC of claim 9, further comprising:

a watchdog timer having a programmable time period for providing a suspend instruction when the IC does not change states for the programmable time period.

12. The IC of claim 9,

wherein the port provided internal to the IC further provides the suspend mode instruction to the configuration block.

13. The IC of claim 9, wherein the suspend mode instruction can be provided from a plurality of signal pins of the IC.