Apparatus and method for channel encoding/decoding in communication system using variable-length LDPC codes

• US 8,261,152 B2
• Filed: 09/10/2008
• Issued: 09/04/2012
• Est. Priority Date: 09/10/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Myung, Seho, Jeong, Hong-Sil, Kim, Jae-Yoel, Yun, Sung-Ryul, Lee, Hak-Ju
• Primary Examiner(s): Baderman, Scott
• Assistant Examiner(s): Leibovich, Yair
• Application Number:
  US12/208,316
• Publication Number:
  US 20090070652A1
• Time in Patent Office: 1,455 Days
• Field of Search: 714/752, 714/758
• US Class Current: 714/752
• CPC Class Codes: H03M 13/1185 wherein the parity-check matrix comprises a part with a double-diagonal
• CPC Class Codes: H03M 13/618 Shortening and extension of codes
• CPC Class Codes: H03M 13/6362 by puncturing
• CPC Class Codes: H03M 13/6393 Rate compatible low-density parity check [LDPC] codes

Abstract

A method and apparatus for generating Low-Density Parity Check (LDPC) codes of various block lengths from a structured LDPC code in a communication system is provided. To support various block lengths, predefined rules are applied to a parity check matrix of an LDPC code, and then shortening is selectively applied to the parity check matrix. Subsequently, if information data bits are input, the input data information bits are encoded into an LDPC codeword by using the parity check matrix according to a preset encoding scheme, and then the encoded LDPC codeword is transmitted after puncturing is selectively applied.

Claims

1. A method of encoding a structured variable-length Low-Density Parity Check (LDPC) code, the method comprising:

detecting, by an encoder, information on a pre-stored first parity check matrix;

identifying, by the encoder, a block length of a LDPC code;

determining, by the encoder, a grouping size for an information word of a second parity check matrix according to the identified block length of the LDPC code;

configuring, by the encoder, submatrices corresponding to the information word of the second parity check matrix from the first parity check matrix in correspondence with the grouping size;

configuring, by the encoder, submatrices corresponding to a parity of the second parity check matrix; and

performing, by the encoder, encoding based on one of the first parity check matrix and the second parity check matrix.

2. The method as claimed in claim 1, wherein the grouping size for the information word of the second parity check matrix is one of a divisor and a multiple of a grouping size for an information word of the first parity check matrix.

3. The method as claimed in claim 1, wherein the configuring of the submatrices corresponding to the information word of the second parity check matrix comprises determining positions including an entry of 1 in the information word of the second parity check matrix by using positions including an entry of 1 in an information word of the first parity check matrix and the grouping size for the information word of the second parity check matrix.

4. The method as claimed in claim 2, wherein, in the configuring of the submatrices corresponding to the information word of the second parity check matrix, row positions including an entry of 1 in a jth column (j=0, 1, 2, . . . , M₂−

1) of an ith column group of the second parity check matrix, S_i,k^(k) (k=1, 2, . . . , D_i), are defined by a following equation;

for i=0,1, . . . ,K₂/M₂−

1 and j=0,1,2, . . . ,M₂−

1,

S_i,0^(k)=R_i,0^(k) mod(N₂−

K₂),k=1,2, . . . ,D_i,

S_i,j^(k)=S_i,(j-1)^(k)+q mod(N₂−

K₂).

5. The method as claimed in claim 1, wherein the configuring of the submatrices corresponding to the parity comprises configuring the submatrices in correspondence with the grouping size.

6. The method as claimed in claim 1, further comprising applying shortening and puncturing to the second parity check matrix.

7. The method as claimed in claim 1, further comprising generating the second parity check matrix corresponding to the block length of the LDPC code.

8. An apparatus for encoding a variable-length Low-Density Parity Check (LDPC) code, the apparatus comprising:

an encoder for identifying a block length of a LDPC code to determine a grouping size for an information word of a second parity check matrix according to the identified block length of the LDPC code, for configuring submatrices corresponding to the information word of the second parity check matrix from a pre-stored first parity check matrix in correspondence with the grouping size;

for configuring submatrices corresponding to a parity of the second parity check matrix, and for performing encoding based on one of the first parity check matrix and the second parity check matrix;

a modulator for modulating the LDPC code into modulation symbols using a preset modulation scheme; and

a transmitter for transmitting the modulation symbols.

9. The apparatus as claimed in claim 8, wherein the grouping size for the information word of the second parity check matrix is one of a divisor and a multiple of a grouping size for an information word of the first parity check matrix.

10. The apparatus as claimed in claim 8, wherein the encoder determines positions including an entry of 1 in the information word of the second parity check matrix by using positions including an entry of 1 in an information word of the first parity check matrix and the grouping size for the information word of the second parity check matrix.

11. The apparatus as claimed in claim 10, wherein the encoder determines row positions including an entry of 1 in a jth column (j=0, 1, 2, . . . , M₂−

1) of an ith column group of the second parity check matrix, S_i,k^(k) (k=1, 2, . . . , D_i), the row positions S_i,k^(k) (k=1, 2, . . . , D_i) being defined by a following equation;

for i=0,1, . . . ,K₂/M₂−

1 and j=0,1,2, . . . ,M₂−

1,

S_i,0^(k)=R_i,0^(k) mod(N₂−

K₂),k=1,2, . . . ,D_i,

S_i,j^(k)=S_i,(j-1)^(k)+q mod(N₂−

K₂).

12. The apparatus as claimed in claim 8, wherein the encoder configures the submatrices corresponding to the parity in correspondence with the grouping size.

13. The apparatus as claimed in claim 8, wherein the encoder applies shortening and puncturing to the second parity check matrix.

14. The apparatus as claimed in claim 8, wherein the second parity check matrix is generated corresponding to the block length of the LDPC code.

15. A method of decoding a structured variable-length Low-Density Parity Check (LDPC) code, the method comprising:

receiving a signal;

detecting information on a pre-stored first parity check matrix;

identifying a block length of an LDPC code to be decoded;

determining a grouping size for an information word of a second parity check matrix according to the identified block length of the LDPC code;

configuring submatrices corresponding to the information word of the second parity check matrix from the first parity check matrix in correspondence with the grouping size;

configuring submatrices corresponding to a parity of the second parity check matrix; and

decoding the received signal into the LDPC code, based on one of the first parity check matrix and the second parity check matrix.

16. The method as claimed in claim 15, further comprising generating the second parity check matrix corresponding to the block length of the LDPC code.

17. An apparatus for decoding a variable-length Low-Density Parity Check (LDPC) code, the apparatus comprising:

a receiver for receiving a signal;

a demodulator for demodulating the received signal using a preset demodulation scheme to output a demodulated signal; and

a decoder for identifying a length of an LDPC code, into which the demodulated signal output from the modulator is decoded, for determining a grouping size for an information word of a second parity check matrix according to the identified block length of the LDPC code, for configuring submatrices corresponding to the information word of the second parity check matrix from a pre-stored first parity check matrix in correspondence with the grouping size and configuring submatrices corresponding to a parity of the second parity check matrix, and for decoding the received signal into the LDPC code, based on one of the first parity check matrix and the second parity check matrix.

18. The apparatus as claimed in claim 17, wherein the second parity check matrix is generated corresponding to the block length of the LDPC code.