Semiconductor device and method for manufacturing the same

• US 8,268,674 B2
• Filed: 08/03/2010
• Issued: 09/18/2012
• Est. Priority Date: 08/08/2007
• Status: Expired due to Fees

• Current Assignee: Teramikros, Inc. (Powertech Technology Inc)
• Original Assignee: Teramikros, Inc. (Powertech Technology Inc)
• Inventors: Jobetto, Hiroyasu
• Primary Examiner(s): Richards, N Drew
• Assistant Examiner(s): SUN, YU-HSI DAVID
• Application Number:
  US12/849,529
• Publication Number:
  US 20100317154A1
• Time in Patent Office: 777 Days
• Field of Search: 257/698, 257/700, 257/E21.532, 438/106, 438/110
• US Class Current: 438/110
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/82047 by mechanical means, e.g. severing, pressing, stamping
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3185 : the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 3/426 : initial plating of through-holes in substrates without metal
• CPC Class Codes: H05K 3/427 : initial plating of through-holes in metal-clad substrates
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

A semiconductor device includes a semiconductor constituent provided with a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. A lower-layer insulating film is provided under and around the semiconductor constituent. A plurality of lower-layer wirings are electrically connected to the electrodes for external connection of the semiconductor constituent, and provided under the lower-layer insulating film. An insulation layer is provided on the lower-layer insulating film in the periphery of the semiconductor constituent. An upper-layer insulating film is provided on the semiconductor constituent and the Insulation layer. A plurality of upper-layer wirings are provided on the upper-layer insulating film. A base plate on which the semiconductor constituent and the insulation layer are mounted is removed.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming a lower-layer insulating film on a base plate;

fixing, on the lower-layer insulating film, a plurality of semiconductor constituents each having a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate;

forming an insulation layer on the lower-layer insulating film at peripheries of the semiconductor constituents and forming an upper-layer insulating film on the semiconductor constituents and the insulation layer;

removing the base plate;

forming lower-layer wirings connected with the electrodes for external connection of the semiconductor constituents under the lower-layer insulating film and forming upper-layer wirings on the upper-layer insulating film; and

obtaining a plurality of semiconductor devices by cutting the lower-layer insulating film, the insulation layer, and the upper-layer insulating film between the semiconductor constituents;

wherein forming the lower-layer insulating film on the base plate includes forming a lower-layer protection metal layer and a lower-layer metallic underlayer on the base plate, and forming the lower-layer insulating film on the lower-layer metallic underlayer; and

wherein removing the base plate includes removing the lower-layer protection metal layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein fixing said plurality of semiconductor constituents on the lower-layer insulating film includes supplying a liquid-form adhesive material onto the lower-layer insulating film in advance and hot-pressing the semiconductor constituents onto the lower-layer insulating film.

3. The method for manufacturing a semiconductor device according to claim 1, wherein fixing said plurality of semiconductor constituents on the lower-layer insulating film includes supplying a sheet-form adhesive material onto the lower-layer insulating film in advance and hot-pressing the semiconductor constituents onto the lower-layer insulating film.

4. The method for manufacturing a semiconductor device according to claim 1, wherein forming the lower-layer wirings and the upper-layer wirings includes forming through holes in the lower-layer insulating film, the insulation layer, and the upper-layer insulating film, and forming vertical conducting units inside the through holes to be connected with the lower-layer wirings and the upper-layer wirings.

5. The method for manufacturing a semiconductor device according to claim 1, further comprising:

forming further lower-layer wirings at peripheries of semiconductor constituent mounting areas on the lower-layer insulating film, and forming further upper-layer wirings under the upper-layer insulating film, the lower-layer wirings being formed to be connected with the further lower-layer wirings, and the upper-layer wirings being formed to be connected with the further upper-layer wirings.

6. The method for manufacturing a semiconductor device according to claim 1, wherein forming the insulation layer and the upper-layer wirings includes arranging a circuit substrate having further lower-layer wirings, further upper-layer wirings, and vertical conducting units which connect the wirings on the insulation layer under the upper-layer wirings at peripheries of the semiconductor constituents, and wherein the lower-layer wirings are formed to be connected to the further lower-layer wirings, and the upper-layer wirings are formed to be connected to the further upper-layer wirings.

7. The method for manufacturing a semiconductor device according to claim 1, wherein the upper-layer insulating film is initially formed under a sub-base plate, and the method further comprises removing the sub-base plate.

8. The method for manufacturing a semiconductor device according to claim 7, wherein forming the upper-layer insulating film on the semiconductor constituents and the insulation layer includes forming an upper-layer protection metal layer and an upper-layer metallic underlayer under the sub-base plate, and forming the upper-layer insulating film under the upper-layer metallic underlayer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein removing the sub-base plate includes removing the upper-layer protection metal layer.

10. The method for manufacturing a semiconductor device according to claim 8, wherein forming the lower-layer insulating film on the lower-layer metallic underlayer includes carrying out surface roughening treatment in advance on an upper surface of the lower-layer metallic underlayer, and forming the upper-layer insulating film under the upper-layer metallic underlayer includes carrying out surface roughening treatment in advance on a lower surface of the upper-layer metallic underlayer.

11. The method for manufacturing a semiconductor device according to claim 1, wherein forming the lower-layer wiring includes forming the lower-layer metallic underlayer, another lower-layer metallic underlayer, and a lower-layer metallic upperlayer by electrolytic plating under the lower-layer insulating film in that order.

12. The method for manufacturing a semiconductor device according to claim 11, wherein forming the upper-layer wiring includes forming an upper-layer metallic underlayer, another upper-layer metallic underlayer, and an upper-layer metallic upperlayer by electrolytic plating on the upper-layer insulating film in that order.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the upper-layer insulating film is initially formed under a sub-base plate and removing the base plate includes removing the sub-base plate;

wherein forming the upper-layer insulating film on the semiconductor constituents and the insulation layer includes forming an upper-layer protection metal layer and the upper-layer metallic underlayer under the sub-base plate, and forming the upper-layer insulating film under the upper-layer metallic underlayer; and

wherein the base plate, the lower-layer metallic underlayer, the another lower-layer metallic underlayer, the lower-layer metallic upperlayer, the sub-base plate, the upper-layer metallic underlayer, the another upper-layer metallic underlayer, and the upper-layer metallic upperlayer are made of copper, and the lower-layer protection metal layer and the upper-layer protection metal layer are made of nickel.

14. A method for manufacturing a semiconductor device, comprising:

forming a lower-layer insulating film on a base plate;

fixing, on the lower-layer insulating film, a plurality of semiconductor constituents each having a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate;

forming a lower-side insulation layer and an upper-side insulation layer on an upper side of the lower-layer insulating film at peripheries of the semiconductor constituents, and providing a circuit substrate having intermediate wirings between the lower-side insulation layer and the upper-side insulation layer, and

forming an upper-layer insulating film on the semiconductor constituents and the upper-side insulation layer;

removing the base plate from the lower-layer insulating film;

forming lower-layer wirings to be connected to electrodes for external connection of the semiconductor constituents and the intermediate wirings of the circuit substrate under the lower-side insulating film, and forming upper-layer wirings to be connected to the intermediate wirings of the circuit substrate on the upper-layer insulating film; and

cutting the lower-layer insulating film, the lower-layer insulation layer, the circuit substrate, the upper-layer insulation layer, and the upper-layer insulating film between the semiconductor constituents, to obtain a plurality of semiconductor devices;

wherein forming the lower-layer insulating film on the base plate includes forming a lower-layer protection metal layer and a lower-layer metallic underlayer on the base plate, and forming the lower-layer insulating film on the lower-layer metallic underlayer; and

wherein removing the base plate includes removing the lower-layer protection metal layer.

15. The method for manufacturing a semiconductor device according to claim 14, wherein the intermediate wirings of the circuit substrate are formed on an upper surface and a lower surface of the circuit substrate, and the circuit substrate has vertical conducting units which connect the intermediate wirings formed on the upper surface and the lower surface.