Semiconductor device and method of forming RF balun having reduced capacitive coupling and high CMRR

• US 8,269,575 B2
• Filed: 03/30/2010
• Issued: 09/18/2012
• Est. Priority Date: 03/30/2010
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Frye, Robert C., Liu, Kai
• Primary Examiner(s): Takaoka, Dean O
• Application Number:
  US12/750,555
• Publication Number:
  US 20110241793A1
• Time in Patent Office: 903 Days
• Field of Search: 333/25, 333/26, 333/238
• US Class Current: 333/25
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A semiconductor device has an RF balun formed over a substrate. The RF balun includes a first conductive trace wound to exhibit inductive properties with a first end coupled to a first terminal of the semiconductor device and second end coupled to a second terminal of the semiconductor device. A first capacitor is coupled between the first and second ends of the first conductive trace. A second conductive trace is wound to exhibit inductive properties with a first end coupled to a third terminal of the semiconductor device and second end coupled to a fourth terminal of the semiconductor device. The first conductive trace is formed completely within the second conductive trace. The first conductive trace and second conductive trace can have an oval, circular, or polygonal shape separated by 50 micrometers. A second capacitor is coupled between the first and second ends of the second conductive trace.

Claims

1. A semiconductor device, comprising:

a substrate; and

a balun formed over the substrate, the balun including,

(a) a first conductive trace wound in a coil to exhibit inductive properties comprising a first end coupled to a first terminal of the semiconductor device and second end coupled to a second terminal of the semiconductor device,

(b) a first capacitor coupled between the first and second ends of the first conductive trace,

(c) a second conductive trace wound in a coil to exhibit inductive properties comprising a first end coupled to a third terminal of the semiconductor device and second end coupled to a fourth terminal of the semiconductor device, the first conductive trace being formed completely within the second conductive trace and separated from the second conductive trace by a distance to reduce inductive and capacitive coupling, and

(d) a second capacitor coupled between the first and second ends of the second conductive trace.

3. The semiconductor device of claim 1, wherein the first conductive trace and second conductive trace each have an oval, circular, or polygonal shape.

5. The semiconductor device of claim 1, further including:

a center tap coupled midway between the first and second ends of the second conductive trace; and

a DC bias coupled to the center tap.

2. A semiconductor device, comprising:

a substrate; and

a balun formed over the substrate, the balun including,

(a) a first conductive trace wound to exhibit inductive properties with a first end coupled to a first terminal of the semiconductor device and second end coupled to a second terminal of the semiconductor device,

(b) a first capacitor coupled between the first and second ends of the first conductive trace,

(c) a second conductive trace wound to exhibit inductive properties with a first end coupled to a third terminal of the semiconductor device and second end coupled to a fourth terminal of the semiconductor device, the first conductive trace being formed completely within the second conductive trace, wherein the first conductive trace and second conductive trace are separated by 50 micrometers.

4. A semiconductor device, comprising:

a substrate; and

a balun formed over the substrate, the balun including,

(a) a first conductive trace wound to exhibit inductive properties with a first end coupled to a first terminal of the semiconductor device and second end coupled to a second terminal of the semiconductor device,

(b) a first capacitor coupled between the first and second ends of the first conductive trace,

(c) a second conductive trace wound to exhibit inductive properties with a first end coupled to a third terminal of the semiconductor device and second end coupled to a fourth terminal of the semiconductor device, the first conductive trace being formed completely within the second conductive trace, wherein the first conductive trace and second conductive trace have a coupling coefficient between 0.2 and 0.45.

6. A semiconductor device, comprising:

a substrate;

an inner conductive trace formed over the substrate and wound to exhibit inductive properties including a first end coupled to a first terminal of the semiconductor device and second end coupled to a second terminal of the semiconductor device; and

an outer conductive trace formed over the substrate and wound to exhibit inductive properties including a first end coupled to a third terminal of the semiconductor device and second end coupled to a fourth terminal of the semiconductor device, the inner conductive trace being formed within the outer conductive trace and separated from the outer conductive trace by a distance to reduce capacitive and inductive coupling.

7. The semiconductor device of claim 6, further including:

a first capacitor formed over the substrate and coupled between the first and second ends of the inner conductive trace; and

a second capacitor formed over the substrate and coupled between the first and second ends of the outer conductive trace.

8. The semiconductor device of claim 6, wherein the inner conductive trace and outer conductive trace are separated by 50 micrometers.

9. The semiconductor device of claim 6, wherein the inner conductive trace and outer conductive trace each have an oval, circular, or polygonal shape.

10. The semiconductor device of claim 6, further including a center tap coupled midway between the first and second ends of the outer conductive trace.

11. The semiconductor device of claim 10, further including a DC bias coupled to the center tap.

12. A semiconductor device, comprising:

a substrate;

a first inductor formed on the substrate; and

a second inductor formed on the substrate, the first inductor being formed within the second inductor and separated from the second inductor by a distance to reduce capacitive coupling.

13. The semiconductor device of claim 12, wherein the first inductor includes a first conductive trace wound to exhibit inductive properties including a first end coupled to a first terminal of the semiconductor device and second end coupled to a second terminal of the semiconductor device.

14. The semiconductor device of claim 13, wherein the second inductor includes a second conductive trace wound to exhibit inductive properties including a first end coupled to a third terminal of the semiconductor device and second end coupled to a fourth terminal of the semiconductor device.

15. The semiconductor device of claim 14, wherein the first conductive trace and second conductive trace are separated by 50 micrometers.

16. The semiconductor device of claim 14, further including:

a first capacitor formed over the substrate and coupled between the first and second ends of the first conductive trace; and

a second capacitor formed over the substrate and coupled between the first and second ends of the second conductive trace.

17. The semiconductor device of claim 14, wherein the first conductive trace and second conductive trace have a coupling coefficient between 0.2 and 0.45.

18. The semiconductor device of claim 14, wherein the first conductive trace and second conductive traces each have an oval, circular, or polygonal shape.

19. The semiconductor device of claim 14, further including:

a center tap coupled midway between the first and second ends of the second conductive trace; and

a DC bias coupled to the center tap.

20. A method of forming a semiconductor device, comprising:

providing a substrate;

forming an inner conductive trace over the substrate and wound to exhibit inductive properties including a first end coupled to a first terminal of the semiconductor device and second end coupled to a second terminal of the semiconductor device; and

forming an outer conductive trace over the substrate and wound to exhibit inductive properties including a first end coupled to a third terminal of the semiconductor device and second end coupled to a fourth terminal of the semiconductor device, the inner conductive trace being formed within the outer conductive trace and separated from the outer conductive trace by a distance to reduce capacitive and inductive coupling.

21. The method of claim 20, further including:

forming a first capacitor formed over the substrate coupled between the first and second ends of the inner conductive trace; and

forming a second capacitor formed over the substrate coupled between the first and second ends of the outer conductive trace.

22. The method of claim 20, wherein the inner conductive trace and outer conductive trace are separated by 50 micrometers.

23. The method of claim 20, wherein the inner conductive trace and outer conductive trace each have an oval, circular, or polygonal shape.

24. The method of claim 20, further including:

providing a center tap coupled midway between the first and second ends of the outer conductive trace; and

connecting a DC bias to the center tap.

25. The method of claim 20, wherein the first conductive trace and second conductive trace have a coupling coefficient between 0.2 and 0.45.