Model for a hardware device-independent method of defining embedded firmware for programmable systems

• US 8,286,125 B2
• Filed: 08/10/2005
• Issued: 10/09/2012
• Est. Priority Date: 08/13/2004
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: McDonald, John, Pearson, Jon, Ogami, Kenneth, Anderson, Doug
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US11/201,922
• Publication Number:
  US 20060033945A1
• Time in Patent Office: 2,617 Days
• Field of Search: 716/1, 716/11, 716 16- 18, 716138-139, 716116-117
• US Class Current: 716/138
• CPC Class Codes: G06F 8/38 for implementing user interfaces

Abstract

A processing device programming system automatically provides a user interface comprising a selectable list of one or more processing devices based on a system level solution, automatically generates an embedded programmable system solution from the system level solution and a processing device selected from the selectable list of one or more processing devices, and automatically programs the processing device according to the embedded programmable system solution.

Claims

1. A method, comprising:

automatically providing a user interface comprising a selectable list of one or more processing devices based on a previously created device-independent system level solution;

providing the user interface with a selectable list of a plurality of high level devices to design the device-independent system level solution;

receiving a selection of a high level device and updating the selectable list of the one or more processing devices after receiving the selection of the high level device from the plurality of high level devices;

automatically generating an embedded programmable system solution from the device-independent system level solution and a processing device selected from the selectable list of one or more processing devices; and

automatically programming the processing device according to the embedded programmable system solution.

2. The method of claim 1, wherein prior to the automatically providing, determining the selectable list of one or more processing devices by matching resource requirements of one or more functions of the device-independent system level solution to one or more base projects associated with the one or more processing devices.

3. The method of claim 2, further comprising automatically generating one or more base projects associated with the one or more processing devices based upon the resource requirements of the one or more functions of the device-independent system level solution and physical parameters associated with the one or more processing devices.

4. The method of claim 1, wherein prior to updating the selectable list of the plurality of high level devices and the selectable list of the one or more processing devices, validating a current state of the device-independent system level solution.

5. The method of claim 4, wherein validating the current state of the device-independent system level solution further comprises:

validating executable expressions associated with a selected high level device;

validating the one or more processing devices by matching resources required by the current state of the device-independent system level solution to the one or more processing devices.

6. The method of claim 1, wherein the selectable list of one or more processing devices is comprised of at least one of a programmable logic device, a field programmable gate array, a micro-controller, a microprocessor-based device, or a circuit comprising a processing device.

7. A system, comprising:

a processing device maker engine configured to provide a user interface comprising a selectable list of one or more processing devices based on a previously created device-independent system level solution, wherein the processing device maker engine is configured to provide the user interface with a selectable list of a plurality of high level devices to design the device-independent system level solution and receive a selection of high level device and update the selectable list of the one or more processing devices after receiving the selection of a high level device from the plurality of high level devices; and

a hardware designer engine configured to receive the device-independent system level solution from the processing device maker and to generate an embedded programmable system solution from the device-independent system level solution and a processing device selected from the one or more processing devices, and to program the processing device according to the embedded programmable system solution.

8. The system of claim 7, wherein to provide the user interface, the processing device maker engine determines the selectable list of one or more processing devices by matching resource requirements of one or more functions of the device-independent system level solution to one or more base projects associated with the one or more processing devices.

9. The system of claim 8, wherein the processing device maker engine is further configured to generate one or more base projects associated with the one or more processing devices based upon the resource requirements of the one or more functions of the device-independent system level solution and physical parameters associated with the one or more processing devices.

10. The system of claim 8, wherein the processing device maker engine is further configured to save a first file comprising the device-independent system level solution, to delete one or more lower level files associated with the embedded programmable system, programmable system, and to generate a schematic of the programmed selected processing device, wherein the schematic includes at least one of functional pins, input output devices, or interfacing circuitry.

11. The system of claim 8, wherein the selectable list of one or more processing devices is comprised of at least one of a programmable logic device, a field programmable gate array, a micro-controller, a microprocessor-based device, or a circuit comprising a processing device.

12. The system of claim 7, wherein prior to the update of the selectable list of the plurality of high level devices and the selectable list of the one or more processing devices, the processing device maker engine is configured to validate a current state of the device-independent system level solution.

13. The system claim 12, wherein to validate the current state of the device-independent system level solution, the processing device maker engine is further configured to validate executable expressions associated with the selected high level devices, and to validate the one or more processing devices by matching resources required by the current state of the device-independent system level solution to the one or more processing devices.

14. A non-transitory machine readable medium having embodied thereon an instruction set, the instruction set being executable by a machine to perform operations comprising:

providing a user interface comprising a selectable list of one or more processing devices based on a previously created device-independent system level solution;

providing the user interface with a selectable list of a plurality of high level devices to design the device-independent system level solution;

receiving a selection of a high level device an updating the selectable list of the one or more processing devices after receiving the selection of the high level device from the plurality of high level devices;

generating an embedded programmable system solution from the device-independent system level solution and a processing device selected from the selectable list of one or more processing devices; and

programming the processing device according to the embedded programmable system solution.

15. The non-transitory machine readable medium of claim 14, wherein prior to updating the selectable list of the plurality of high level devices and the selectable list of the one or more processing devices, validating a current state of the device-independent system level solution.

16. The non-transitory machine readable medium of claim 15, wherein validating the current state of the device-independent system level solution further comprises:

validating executable expressions associated with a selected high level device; and

validating the one or more processing devices by matching resources required by the current state of the device-independent system level solution to the one or more processing devices.