Solid-state memory device, data processing system, and data processing device

• US 8,295,080 B2
• Filed: 06/04/2010
• Issued: 10/23/2012
• Est. Priority Date: 06/11/2009
• Status: Expired due to Fees

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Aizawa, Kazuo, Asano, Isamu, Tominaga, Junji, Kolobov, Alexander, Fons, Paul, Simpson, Robert
• Primary Examiner(s): Sofocleous, Alexander
• Assistant Examiner(s): Byrne, Harry W
• Application Number:
  US12/794,077
• Publication Number:
  US 20100315867A1
• Time in Patent Office: 872 Days
• Field of Search: 365/46, 365/94, 365/100, 365/113, 365/129, 365/148, 365/163, 257 2- 5, 257/9, 257/296, 257/310, 257/E21.35, 257/E31.047, 257/E27.006, 438/29, 438/95, 438/96, 438/166, 438/135, 438/240, 438/259, 438/365, 438/482, 438/486, 438/597, 438/785, 977/754
• US Class Current: 365/163
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10N 70/023 by chemical vapor deposition, e.g. MOCVD, ALD
• CPC Class Codes: H10N 70/026 by physical vapor deposition, e.g. sputtering
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/066 by filling of openings, e.g. damascene method
• CPC Class Codes: H10N 70/235 between different crystalline phases, e.g. cubic and hexagonal
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A solid-state memory device includes: a superlattice laminate having plural crystal layers laminated therein, the crystal layers including first and second crystal layers having mutually opposite compositions; a lower electrode provided on a first surface in a laminating direction of the superlattice laminate; and an upper electrode provided on a second surface of the superlattice laminate in the laminating direction. The first crystal layer included in the superlattice laminate is made of a phase change compound. According to the present invention, the superlattice laminate laminated in opposite directions of the upper and lower electrodes is sandwiched between these electrodes. Therefore, when an electric energy is applied to the superlattice laminate via these electrodes, a uniform electric energy can be applied to a laminated surface of the superlattice laminate. Accordingly, fluctuation of a resistance is small even when information is repeatedly rewritten, and data can be read stably as a result.

Claims

1. A solid-state memory device comprising:

first and second electrodes arranged to a first direction; and

a superlattice laminate sandwiched between the first and second electrodes, the superlattice laminate having a plurality of crystal layers laminated one another, the crystal layers including first and second crystal layers having mutually different compositions, wherein

at least a part of the superlattice laminate has an interface of the first and second crystal layers that intersects with the first direction, and

the first crystal layer included in the superlattice laminate comprises a phase change material.

2. The solid-state memory device as claimed in claim 1, further comprising a first interlayer insulation film in which the first electrode is embedded, wherein

the superlattice laminate is provided on the first interlayer insulation film.

3. The solid-state memory device as claimed in claim 2, further comprising a sidewall insulation film that covers an inner wall of a first through-hole formed in the first interlayer insulation film, wherein

the first electrode is provided in a region surrounded by the sidewall insulation film.

4. The solid-state memory device as claimed in claim 2, wherein a laminated surface of the superlattice laminate is a flat surface.

5. The solid-state memory device as claimed in claim 2, further comprising a second interlayer insulation film provided on the first interlayer insulation film, wherein

the second interlayer insulation film has a second through-hole, and

a laminated surface of the superlattice laminate is provided along a bottom surface and an inner wall of the second through-hole.

6. The solid-state memory device as claimed in claim 5, wherein at least a part of the second electrode is provided in a region surrounded by the superlattice laminate.

7. The solid-state memory device as claimed in claim 5, wherein the second through-hole is filled with the superlattice laminate.

8. The solid-state memory device as claimed in claim 5, wherein the second through-hole has a tapered shape such that an internal diameter becomes smaller toward the first electrode.

9. The solid-state memory device as claimed in claim 1, further comprising:

a first interlayer insulation film having a first through-hole; and

a sidewall insulation film that covers an inner wall of the first through-hole, wherein

the first electrode and the superlattice laminate are provided in a region surrounded by the sidewall insulation film.

10. The solid-state memory device as claimed in claim 1, wherein at least apart of the second electrode has a convex shape such that a diameter becomes smallest at a portion nearest the first electrode.

11. The solid-state memory device as claimed in claim 1, further comprising a protection insulation film that covers an end surface in a direction along a laminated surface of the superlattice laminate.

12. The solid-state memory device as claimed in claim 1, wherein the first crystal layer included in the superlattice laminate has a crystal state reversibly changed by an electric energy given from the first and second electrodes.

13. The solid-state memory device as claimed in claim 1, wherein the first crystal layer included in the superlattice laminate has positions of constituent atoms reversibly replaced by an electric energy given from the first and second electrodes.

14. The solid-state memory device as claimed in claim 13, wherein the first crystal layer comprises a chalcogen compound containing germanium (Ge) and tellurium (Te) as main components.

15. The solid-state memory device as claimed in claim 14, wherein the first crystal layer comprises a chalcogen compound containing germanium (Ge) and tellurium (Te) at a rate of substantially 1:

1, and a crystal state of the first crystal layer is reversibly transited between a first crystal structure in which one germanium atom is orientated to four tellurium atoms and a second crystal structure in which one germanium atom is orientated to six tellurium atoms, based on a movement of a germanium atom due to energy application.

16. The solid-state memory device as claimed in claim 13, wherein the second crystal layer comprises a chalcogen compound containing antimony (Sb) and tellurium (Te) as main components.

17. The solid-state memory device as claimed in claim 16, wherein

the superlattice laminate has a configuration such that the first crystal layer and the second crystal layer are alternately laminated repeatedly at plural times, and

among the second crystal layers, a second crystal layer nearest the first electrode has a larger film thickness than that of other second crystal layers.

18. The solid-state memory device as claimed in claim 13, further comprising:

a write circuit that moves a position of a constituent atom of the first crystal layer by flowing a write current to the superlattice laminate via the first and second electrodes; and

a read circuit that flows a read current to the superlattice laminate via the first and second electrodes without moving a position of a constituent atom of the first crystal layer.

19. The solid-state memory device as claimed in claim 18, wherein the write circuit includes a set circuit that causes the first crystal layer to change from a first crystal structure to a second crystal structure, and a reset circuit that causes the first crystal layer to change from the second crystal structure to the first crystal structure.

20. The solid-state memory device as claimed in claim 1, further comprising a switching device electrically connected to the first electrode, wherein

the switching device comprises a vertical MOS transistor having a silicon pillar that serves as a channel region, and

the silicon pillar is projected in a direction perpendicular to a main surface of a semiconductor substrate.

21. The solid-state memory device as claimed in claim 1, further comprising a switching device electrically connected to the first electrode, wherein

the switching device comprises a diode having at least one of an anode and a cathode being formed in a silicon pillar, and

the silicon pillar is projected in a direction perpendicular to a main surface of a semiconductor substrate.

22. A data processing system comprising:

a solid-state memory device;

a data processor; and

a system bus that connects the solid-state memory device to the data processor,

wherein a memory cell included in the solid-state memory device comprises;

first and second electrodes arranged to a first direction; and

a superlattice laminate sandwiched between the first and second electrodes, the superlattice laminate having a plurality of crystal layers laminated one another, the crystal layers including first and second crystal layers having mutually different compositions, wherein

at least a part of the superlattice laminate has an interface of the first and second crystal layers that intersects with the first direction, and

the first crystal layer included in the superlattice laminate comprises a phase change material.

23. A solid-sate memory comprising:

a data-rewritable user area; and

a defective-address storing circuit that stores a defective address included in the user area,

wherein a memory cell included in the defective-address storing circuit comprises;

first and second electrodes arranged to a first direction; and

a superlattice laminate sandwiched between the first and second electrodes, the superlattice laminate having a plurality of crystal layers laminated one another, the crystal layers including first and second crystal layers having mutually different compositions, wherein

at least a part of the superlattice laminate has an interface of the first and second crystal layers that intersects with the first direction, and

the first crystal layer included in the superlattice laminate comprises a phase change material.

24. A data processing device comprising:

a program area; and

a data processing circuit that performs a predetermined operation in accordance with a program stored in the program area,

wherein a memory cell included in the program area comprises;

first and second electrodes arranged to a first direction; and

a superlattice laminate sandwiched between the first and second electrodes, the superlattice laminate having a plurality of crystal layers laminated one another, the crystal layers including first and second crystal layers having mutually different compositions, wherein

at least a part of the superlattice laminate has an interface of the first and second crystal layers that intersects with the first direction, and

the first crystal layer included in the superlattice laminate comprises a phase change material.