Current-controlled CMOS logic family

• US 8,299,834 B2
• Filed: 05/28/2010
• Issued: 10/30/2012
• Est. Priority Date: 06/28/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Hairapetian, Armond
• Primary Examiner(s): Nguyen, Hai L
• Application Number:
  US12/789,469
• Publication Number:
  US 20100237921A1
• Time in Patent Office: 886 Days
• Field of Search: 341/100, 341/101, 327/210, 327/211, 327/407, 327/408, 327/415, 327/416
• US Class Current: 327/210
• CPC Class Codes: H03K 17/04 Modifications for accelerating switching
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 17/04163 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence
• CPC Class Codes: H03K 19/215 using field-effect transistors
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 3/356043 with synchronous operation
• CPC Class Codes: H03K 3/356139 with synchronous operation
• CPC Class Codes: H03K 3/3562 of the master-slave type

Abstract

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C³MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C³MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C³MOS logic with low power conventional CMOS logic. The combined C³MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Claims

1. An apparatus, comprising:

a circuit block, including current-controlled complementary metal-oxide semiconductor (C³MOS) logic, for deserializing a serialized signal thereby generating a deserialized signal including a plurality of signals, wherein;

the C³MOS logic including a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source;

a current steering circuit within the C³MOS circuit including the first source and the second source;

the first source and the second source being coupled together and to a current source; and

the first drain and the second drain being coupled to a power supply.

2. The apparatus of claim 1, wherein:

the serialized signal and the plurality of signals being electrical signals including data compliant with a fiber channel.

3. The apparatus of claim 1, wherein:

the serialized signal having a first frequency; and

each of the plurality of signals having a second frequency.

4. The apparatus of claim 3, wherein:

the first frequency being greater than the second frequency.

5. The apparatus of claim 3, wherein:

the first frequency being an integer multiple of the second frequency.

6. The apparatus of claim 1, further comprising:

a processing circuit block, coupled to the circuit block and including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, for generating a plurality of processed signals.

7. The apparatus of claim 6, wherein:

the CMOS logic being coupled to a first power supply; and

the C³MOS logic being coupled to a second power supply.

8. The apparatus of claim 1, wherein:

the first source and second source being coupled to at least one additional power supply via the current source.

9. The apparatus of claim 1, wherein:

the first source and the second source being coupled together and to a first node of the current source; and

a second node of the current source being grounded.

10. The apparatus of claim 1, wherein:

the apparatus being an integrated circuit; and

the serialized signal being provided to the integrated circuit from off-chip.

11. The apparatus of claim 1, wherein:

current steering is performed within the current steering circuit in response to the serialized signal, being a differential signal, provided to the first gate and the second gate.

12. The apparatus of claim 1, wherein:

the first drain being coupled to the power supply via a first resistive load; and

the second drain being coupled to the power supply via a second resistive load.

13. An apparatus, comprising:

a circuit block, including current-controlled complementary metal-oxide semiconductor (C³MOS) logic, for serializing a plurality of signals thereby generating a serialized signal, wherein;

the C³MOS logic including a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source;

a current steering circuit within the C³MOS circuit including the first source and the second source;

the first source and the second source being coupled together and to a current source; and

the first drain and the second drain being coupled to a power supply.

14. The apparatus of claim 13, wherein:

the serialized signal and the plurality of signals being electrical signals including data compliant with a fiber channel.

15. The apparatus of claim 13, wherein:

the serialized signal having a first frequency; and

each of the plurality of signals having a second frequency.

16. The apparatus of claim 15, wherein:

the first frequency being greater than the second frequency.

17. The apparatus of claim 15, wherein:

the first frequency being an integer multiple of the second frequency.

18. The apparatus of claim 13, further comprising:

a processing circuit block, coupled to the circuit block and including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, for providing the plurality of signals.

19. The apparatus of claim 18, wherein:

the CMOS logic being coupled to a first power supply; and

the C³MOS logic being coupled to a second power supply.

20. The apparatus of claim 13, wherein:

the first source and second source being coupled to at least one additional power supply via the current source.

21. The apparatus of claim 13, wherein:

the first source and the second source being coupled together and to a first node of the current source; and

a second node of the current source being grounded.

22. The apparatus of claim 13, wherein:

the apparatus being an integrated circuit; and

the serialized signal being provided off-chip from the integrated circuit.

23. The apparatus of claim 13, wherein:

current steering is performed within the current steering circuit in response to at least one of the plurality of signals, being a differential signal, provided to the first gate and the second gate.

24. The apparatus of claim 13, wherein:

the first drain being coupled to the power supply via a first resistive load; and

the second drain being coupled to the power supply via a second resistive load.

25. An apparatus, comprising:

a first circuit block, including first current-controlled complementary metal-oxide semiconductor (C³MOS) logic, for deserializing a first serialized signal thereby generating a deserialized signal including a plurality of signals;

a processing circuit block, coupled to the first circuit block and including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, for generating a plurality of processed signals; and

a second circuit block, coupled to the processing circuit block and including second C³MOS logic, for serializing the plurality of processed signals thereby generating a second serialized signal, wherein;

the first C³MOS logic including a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source;

a first current steering circuit within the C³MOS circuit including the first source and the second source;

the first source and the second source being coupled together and to a first current source;

the first drain and the second drain being coupled to a power supply;

the second C³MOS logic including a third MOS transistor with a third drain, a third gate, and a third source and a fourth MOS transistor with a fourth drain, a fourth gate, and a fourth source, wherein;

a second current steering circuit including the third source and the fourth source;

the third source and the fourth source being coupled together and to the second current source; and

the third drain and the fourth drain being coupled to the power supply.

26. The apparatus of claim 25, wherein:

the first serialized signal, the plurality of processed signals, and the second serialized signal being electrical signals including data compliant with a fiber channel.

27. The apparatus of claim 25, wherein:

the first serialized signal having a first frequency;

each of the plurality of processed signals having a second frequency; and

the second serialized signal having a third frequency.

28. The apparatus of claim 27, wherein:

each of the first frequency and the third frequency being greater than the second frequency.

29. The apparatus of claim 27, wherein:

each of the first frequency and the third frequency being an integer multiple of the second frequency.

30. The apparatus of claim 25, wherein:

the CMOS logic being coupled to a first power supply; and

each of the first C³MOS logic and the second C³MOS logic being coupled to a second power supply.

31. The apparatus of claim 25, wherein:

the first source and second source being coupled to at least one additional power supply via the first current source; and

the third source and fourth source being coupled to the at least one additional power supply via the second current source.

32. The apparatus of claim 25, wherein:

the first source and the second source being coupled together and to a first node of the first current source; and

a second node of the first current source being grounded;

the third source and the fourth source being coupled together and to a first node of the second current source; and

a second node of the second current source being grounded.

33. The apparatus of claim 25, wherein:

the apparatus being an integrated circuit; and

the first serialized signal being provided to the integrated circuit from off-chip.

34. The apparatus of claim 25, wherein:

current steering is performed within the first current steering circuit in response to the first serialized signal, being a first differential signal, provided to the first gate and the second gate; and

current steering is performed within the second current steering circuit in response to the second serialized signal, being a second differential signal, provided to the third gate and the fourth gate.