Staggered reset in CMOS digital sensor device
First Claim
1. A system that staggers resets of rows of pixels in a complementary metal-oxide-semiconductor (CMOS) imaging system-on-chip (iSoC) sensor, comprising:
- a reset component that sends reset signals to reset transistors of pixels included in a pixel array to reset the pixels;
a select component that transfers select signals to select transistors of the pixels included in the pixel array to readout values from the pixels; and
a signal timing component that controls timing of the reset component and the select component to coordinate transferring reset signals and select signals to the pixels, wherein when employing sub-frame integration, a first select signal is transferred at a first time period, a first reset signal is transferred at a second time period, a second select signal is transferred at a third time period, and a second reset signal is sent at a fourth time period, such that disparate rows of pixels in the pixel array are reset at different, non-intersecting time periods during a unique readout time interval, wherein the unique readout time is not longer than a time needed to integrate one frame and the first time period, the second time period, the third time period and the fourth time period are non-overlapping.
2 Assignments
0 Petitions
Accused Products
Abstract
Systems and methods are provided that facilitate staggering resets of rows of pixels in a CMOS imaging iSoC sensor. Reset signals and select signals can be provided to pixels in a pixel array in a coordinated manner when employing full frame integration or sub-frame integration. Further, reset signals and select signals can be transferred to a first row of pixels, while reset signals can be transferred to a second row of pixels during a unique readout time interval when utilizing sub-frame integration. Within the unique readout time interval, reset signals can be transferred to the first row of pixels during a first time period, while reset signals can be transferred to the second row of pixels during a second time period, where the first and second time periods are non-overlapping. Accordingly, cross-talk between rows of pixels during reset can be mitigated, which leads to enhanced uniformity.
12 Citations
16 Claims
-
1. A system that staggers resets of rows of pixels in a complementary metal-oxide-semiconductor (CMOS) imaging system-on-chip (iSoC) sensor, comprising:
-
a reset component that sends reset signals to reset transistors of pixels included in a pixel array to reset the pixels; a select component that transfers select signals to select transistors of the pixels included in the pixel array to readout values from the pixels; and a signal timing component that controls timing of the reset component and the select component to coordinate transferring reset signals and select signals to the pixels, wherein when employing sub-frame integration, a first select signal is transferred at a first time period, a first reset signal is transferred at a second time period, a second select signal is transferred at a third time period, and a second reset signal is sent at a fourth time period, such that disparate rows of pixels in the pixel array are reset at different, non-intersecting time periods during a unique readout time interval, wherein the unique readout time is not longer than a time needed to integrate one frame and the first time period, the second time period, the third time period and the fourth time period are non-overlapping. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A system that staggers resets of rows of pixels in a CMOS imaging system-on-chip (iSoC) sensor, comprising:
-
a reset component that sends reset signals to reset transistors of pixels included in a pixel array to reset the pixels; a select component that transfers select signals to select transistors of the pixels included in the pixel array to readout values from the pixels; and a signal timing component that controls timing of the reset component and the select component to coordinate transferring reset signals and select signals to the pixels, wherein the signal timing component coordinates; transmitting a first select signal to pixels in the first row during a time period prior to sending a first reset signal to pixels in a first row corresponding to a read pointer during a first time period within a unique readout time interval; transmitting a second select signal to pixels in the first row during a time period subsequent to sending the first reset signal; and sending a second reset signal to pixels in a second row corresponding to a reset pointer during a second time period within the unique readout time interval while operating in sub-frame integration mode, wherein the first time period and the second time period are non-overlapping to stagger the first reset signal and the second reset signal and the first select signal initiates reading values from pixels in the first row and the second select signal causes reading of reset values from pixels in the first row.
-
-
13. A method that facilitates staggering resets for sub-frame integration in a CMOS sensor imager, comprising:
-
sending a first select signal to a first set of pixels in a first row corresponding to a read pointer during a first time period within a unique readout time interval to read respective values from pixels in the first set, wherein the unique readout time interval is not longer than a time need to integrate one frame; transferring a first reset signal to the first set of pixels in the first row during a second time period within the unique readout time interval to reset pixels in the first set; transmitting a second reset signal to a second set of pixels in a second row corresponding to a reset pointer during a third time period within the unique readout time interval to reset pixels in the second set; and conveying a second select signal to the first set of pixels in the first row during a fourth time period within the unique readout time interval to readout respective reset values from pixels in the first set, wherein the first time period, the second time period, the third time period, and the fourth time period are non-overlapping. - View Dependent Claims (14, 15)
-
-
16. A method that facilitates staggering resets for sub-frame integration in a CMOS sensor imager, comprising:
-
sending a first select signal to a first set of pixels in a first row corresponding to a read pointer during a first time period within a unique readout time interval to read respective values from pixels in the first set, wherein the unique readout time interval is not longer than a time need to integrate one frame; transferring a first reset signal to the first set of pixels in the first row during a second time period within the unique readout time interval to reset pixels in the first set; transmitting a second reset signal to a second set of pixels in a second row corresponding to a reset pointer during a third time period within the unique readout time interval to reset pixels in the second set; and conveying a second select signal to the first set of pixels in the first row during a fourth time period within the unique readout time interval to readout respective reset values from pixels in the first set; ordering transmission of signals within the unique readout time interval to cause the first select signal to be sent first, the first reset signal transferred second, the second reset signal transmitted third, and the second select signal conveyed fourth.
-
Specification