System for pipelined processing

• US 8,300,988 B2
• Filed: 12/17/2008
• Issued: 10/30/2012
• Est. Priority Date: 07/30/1999
• Status: Expired due to Fees

• Current Assignee: DBEZ Firenze LLC (SoftBank Group Corp.)
• Original Assignee: G&H Nevada-Tek
• Inventors: Miner, Paul, Gough, Michael L.
• Primary Examiner(s): Tran, Phuoc
• Application Number:
  US12/337,599
• Publication Number:
  US 20090123080A1
• Time in Patent Office: 1,413 Days
• Field of Search: 382/303, 382/307
• US Class Current: 382/303
• CPC Class Codes: G06T 9/00 Image coding bandwidth or redundancy reduction for static pictures H04N1/41; coding or decoding of static colour picture signals H04N1/64; methods or arrangements for coding, decoding, compressing or decompressing digital video signals H04N19/00
• CPC Class Codes: H04N 19/12 Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
• CPC Class Codes: H04N 19/156 Availability of hardware or computational resources, e.g. encoding based on power-saving criteria
• CPC Class Codes: H04N 19/176 the region being a block, e.g. a macroblock
• CPC Class Codes: H04N 19/18 the unit being a set of transform coefficients
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/46 Embedding additional information in the video signal during the compression process H04N19/517, H04N19/68, H04N19/70 take precedence
• CPC Class Codes: H04N 19/60 using transform coding
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

An example embodiment includes a processor module, a pipe analyzer and a central processing unit. The processor module extracts a plurality of components from an input bit stream by extracting predetermined n-bits at a time from the input bit stream and analyzing the n-bits for components. The central processing unit has at least two pipelines for receiving the components derived from the input bit stream. The pipe analyzer is coupled between the processor module and the central processing unit for analyzing the components of the input bit stream and directing each of the components into a suitable pipeline of the central processing unit based on the analysis the pipe analyzer.

Claims

1. A system for pipelined processing comprising:

a processor module implementing a method for extracting a plurality of components from an input bit stream by extracting a predetermined n-bits at a time from the input bit stream and analyzing the n-bits for components;

a central processing unit having at least two pipelines for receiving the components of the input bit stream for processing purposes; and

a pipe analyzer coupled between the processor module and the central processing unit implementing a method for analyzing the components of the input bit stream and directing each of the components into a suitable pipeline of the central processing unit based on the analysis, the pipe analyzer utilizing a look-up table having a plurality of associated parallel processing code segments.

2. The system as set forth in claim 1 wherein at least one of the processor module and the pipe analyzer comprises hardware.

3. The system as set forth in claim 2 wherein said hardware is a part of said central processing unit.

4. The system as set forth in claim 1 wherein the method of said processor module and the method of said pipe analyzer are implemented in software.

5. The system as set forth in claim 4 wherein said software is executed by a computer system.

6. The system as set forth in claim 5 wherein the computer system includes memory in which program instructions comprising software may be at least temporarily stored.

7. A computer implemented process including code segments stored in digital memory of a computer for managing input data for parallel processing comprising:

code segments for extracting a plurality of components from an input bit stream; and

code segments for analyzing the components of the input bit stream using a look-up table and assigning each component a suitable pipeline for parallel processing;

wherein said look-up table includes a plurality of associated parallel processing code segments.