Pipeline configuration protocol and configuration unit communication

  • US 8,301,872 B2
  • Filed: 05/04/2005
  • Issued: 10/30/2012
  • Est. Priority Date: 06/13/2000
  • Status: Expired due to Term
First Claim
Patent Images

1. A microprocessor chip comprising:

  • a plurality of processor cores;

    a cache system including multiple levels, including at least (a) a first cache level that includes at least one cache and (b) at least one superior cache level including a plurality of same level cache nodes each including an internal cache memory; and

    a bus system;

    wherein;

    for each of at least one of the plurality of processor cores, a respective cache of the first cache level is assigned and dedicated to the respective processor core, to exclusion of the others of the plurality of processor cores;

    the bus system includes segments interconnecting, at least one of directly and indirectly, at least the plurality of same level cache nodes (i) to each other and (ii) to the plurality of processor cores;

    each of the plurality of same level cache nodes is communicatively connectable with each of the plurality of processor cores via the bus system for transferring data between the respective cache node and respective processor core;

    a highest of the multiple levels is connected to a higher level memory;

    the segments of the bus system are arbitrated for data transfer;

    the bus system transmits a protocol for requesting and granting access to segments for data transfer; and

    for each of at least one of the plurality of cache nodes;

    the bus system includes a path to another of the plurality of same level cache nodes that is to a right of the respective cache node and a path to another of the plurality of same level cache nodes that is to a left of the respective cache node; and

    a connection from the respective cache node to one of the plurality of processor cores is provided.

View all claims
    ×
    ×

    Thank you for your feedback

    ×
    ×