Method and apparatus for a computing system having an active sleep mode CPU that uses the cache of a normal active mode CPU

• US 8,301,916 B2
• Filed: 06/08/2010
• Issued: 10/30/2012
• Est. Priority Date: 08/14/2002
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hamilton, Tony G.
• Primary Examiner(s): Tran, Vincent
• Application Number:
  US12/796,604
• Publication Number:
  US 20100250989A1
• Time in Patent Office: 875 Days
• Field of Search: 713300-375
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2360/06 Use of more than one graphics processor to process data before displaying to one or more screens
• CPC Class Codes: G09G 5/36 characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method is described that involves storing active sleep mode software instructions to be executed by a low end central processing unit into an on chip cache that caches normal active mode software instructions executed by a high end central processing unit. The active sleep mode software instructions are to be executed by the low end central processing unit during an active sleep mode. The normal active mode software instructions are executed by the high end central processing unit during a normal active mode. The active sleep mode consumes less power than the normal active mode.

Claims

1. An apparatus, comprising:

a first processor unit to operate in a first, higher power mode;

a second processor unit to operate in a second, lower power mode, the second processor unit to have access to a lesser number of available instructions than the first processor unit;

a main memory to store instructions to be executed by the first processor unit;

a memory cache that is accessible to the first and second processor units, wherein the memory cache stores instructions to be executed by the second processor unit in the second, lower power mode and the second processor unit and memory cache to be active when the first processor unit and main memory are not active.

2. The apparatus of claim 1 wherein said memory cache is part of the first processor unit.

3. The apparatus of claim 1 wherein said first processor unit and second processor unit share at least one I/O component.

4. The apparatus of claim 3 wherein said at least one I/O component comprises a wireless interface.

5. The apparatus of claim 4 wherein said at least one I/O component further comprises a nonvolatile data storage device.

6. The apparatus of claim 1, wherein the second processor unit is configured to receive information wirelessly in the second, lower power mode.

7. The apparatus of claim 6, wherein the second processor unit is configured to decompress the information received in the second, lower power mode.

8. The apparatus of claim 6, wherein the second processor unit is configured to transfer the information received to the memory cache in the second, lower power mode.

9. The apparatus of claim 1, further comprising a display to be active in the second, lower power mode to display information through the second processor unit.

10. The apparatus of claim 9, wherein the display is configured to consume less power when active in the second, lower power mode than a display configured to be active in the first, higher power mode.

11. The apparatus of claim 10, in which the same display is used in both the first and second modes.