DRAM memory cell having a vertical bipolar injector

• US 8,305,803 B2
• Filed: 11/09/2010
• Issued: 11/06/2012
• Est. Priority Date: 01/14/2010
• Status: Active Grant

• Current Assignee: Soitec S.A.
• Original Assignee: Soitec S.A.
• Inventors: Ferrant, Richard, Mazure, Carlos
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): RADKE, JAY W
• Application Number:
  US12/942,754
• Publication Number:
  US 20110170343A1
• Time in Patent Office: 728 Days
• Field of Search: 365/174, 365/177, 365/184, 257/273, 257/347, 257/408
• US Class Current: 365/177
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 27/0711 in combination with bipolar transistors and diodes, or capacitors, or resistors
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/7302 structurally associated with other devices assemblies of devices H01L25/00; integrated circuits H01L27/00; IGBT H01L29/7393
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

The invention relates to a memory cell having an FET transistor with a source, a drain and a floating body between the source and the drain, and an injector that can be controlled to inject a charge into the floating body of the FET transistor. The injector includes a bipolar transistor having an emitter, a base and a collector formed by the body of the FET transistor. Specifically, in the memory cell, the emitter of the bipolar transistor is arranged so that the source of the FET transistor serves as the base for the bipolar transistor. The invention also includes a memory array comprising a plurality of memory cells according to the first aspect of the invention, and to methods of controlling such memory cells.

Claims

1. A memory cell comprising:

a horizontal FET transistor having a source connected to a source line, a drain connected to a bit line and a floating body between the source and the drain; and

an injector that can be controlled to inject a charge into the floating body of the FET transistor, the injector comprising a bipolar transistor having an emitter connected to an injection line, a base and a collector formed by the floating body of the FET transistor, with the injection line running below the surface of the memory cell;

wherein the emitter of the bipolar transistor is arranged so that the emitter/source assembly forms a vertical stack, the source of the FET transistor serving as the base for the bipolar transistor.

2. The memory cell of claim 1, in which the emitter is integrated in the source.

5. The memory cell of claim 2, in which the emitter is arranged in a top region of the source.

8. The memory cell of claim 1, in which the emitter is arranged below the source.

10. The memory cell of claim 1, in which the FET transistor also comprises a gate electrode recessed in the floating body and insulated from the latter by a dielectric layer.

11. The memory cell of claim 1, in which the emitter comprises a doped semiconductive material of conductivity opposite to that of the source.

12. The memory cell of claim 1, further comprising a buried insulating layer.

13. The memory cell of claim 1, in which the FET transistor is formed in a well produced in the top part of a bulk substrate.

15. A memory array comprising a plurality of memory cells according claim 1.

16. A memory array according to claim 15 further comprising a source line coupled to the source of each memory cell along a column of the array and an injection line parallel to the source line coupled to the emitter of each memory cell along said column.

18. A method of controlling a memory cell of claim 1 to program a logic 1 state comprising:

applying a positive voltage with a magnitude less than or equal to about the nominal power supply voltage to the drain of the FET transistor;

applying a positive voltage to the injector; and

applying about a nominal power supply voltage to the gate of the FET transistor.

19. A method of controlling a memory cell of claim 1 to program a logic 0 state comprising:

applying a negative voltage with a magnitude less than or equal to about the nominal power supply voltage to the drain of the FET transistor; and

applying about a nominal power supply voltage to the gate of the FET transistor.

3. A memory cell comprising:

a horizontal FET transistor having a source connected to a source line, a drain connected to a bit line and a floating body between the source and the drain; and

an injector that can be controlled to inject a charge into the floating body of the FET transistor, the injector comprising a bipolar transistor having an emitter connected to an injection line, a base and a collector formed by the floating body of the FET transistor;

wherein the emitter of the bipolar transistor is arranged in a bottom region of the source so that the emitter/source assembly forms a vertical stack, the source of the FET transistor serving as the base for the bipolar transistor.

4. The memory cell of claim 3, in which the source comprises a strongly doped central region and a lightly doped peripheral region surrounding the central region, and in which the emitter is arranged within the peripheral region of the source under the central region of the source.

6. A memory cell comprising:

a horizontal FET transistor having a source connected to a source line, a drain connected to a bit line and a floating body between the source and the drain; and

an injector that can be controlled to inject a charge into the floating body of the FET transistor, the injector comprising a bipolar transistor having an emitter connected to an injection line, a base and a collector formed by the floating body of the FET transistor;

wherein the emitter of the bipolar transistor is arranged in a top region of the source so that the emitter/source assembly forms a vertical stack, the source of the FET transistor serving as the base for the bipolar transistor, and

wherein the source comprises a lightly doped top region and a strongly doped bottom region arranged below the top region, and in which the emitter is integrated in the top region.

7. The memory cell of claim 6, in which the bottom region of the source is arranged below a buried insulating layer and is linked to the top region of the source via a connecting passage extending through the insulating layer.

9. A memory cell comprising:

a horizontal FET transistor having a source connected to a source line, a drain connected to a bit line and a floating body between the source and the drain; and

an injector that can be controlled to inject a charge into the floating body of the FET transistor, the injector comprising a bipolar transistor having an emitter connected to an injection line, a base and a collector formed by the floating body of the FET transistor;

wherein the emitter of the bipolar transistor is arranged below a buried insulating layer and is linked to the source via a connecting passage extending through the insulating layer so that the emitter/source assembly forms a vertical stack, the source of the FET transistor serving as the base for the bipolar transistor.

20. A memory array comprising a plurality of memory cells according claim 9.

14. A memory cell comprising:

a FET transistor having a source, a drain and a floating body between the source and the drain; and

an injector that can be controlled to inject a charge into the floating body of the FET transistor, the injector comprising a bipolar transistor having an emitter, a base and a collector formed by the floating body of the FET transistor,

wherein the emitter is connected to an injection line that runs below the surface of the memory cell.

17. A memory array comprising a plurality of memory cells according claim 14.