Method and apparatus for dynamic power management control using serial bus management protocols

• US 8,312,299 B2
• Filed: 03/26/2009
• Issued: 11/13/2012
• Est. Priority Date: 03/28/2008
• Status: Expired due to Fees

• Current Assignee: Packet Digital, LLC
• Original Assignee: Packet Digital, LLC
• Inventors: Tremel, Christopher J., Morlock, Brian M., Schmitz, Michael J.
• Primary Examiner(s): Zaman, Faisal M
• Application Number:
  US12/411,932
• Publication Number:
  US 20090249089A1
• Time in Patent Office: 1,328 Days
• Field of Search: 713/300, 713/320, 713/322, 713/323, 713/324
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/325 Power saving in peripheral device
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus for on-demand power management includes an I/O serial communication master device, peripheral devices that communicate with the master device along the serial bus, and a power manager that buffers the peripheral devices from the serial communication master. The power manager also manages voltage regulation and clock sources to the peripheral devices, with the ability of placing the peripheral devices in an inactive state, or in any number of active states as a means to conserve energy. In some embodiments, the I/O serial communications master acts as if the peripheral devices are always in the highest activity state, and the power manager manages the communications to and from the peripheral devices and the power management of the peripheral devices to minimize energy consumption and reduce system latency.

Claims

1. A computer-implemented method, comprising:

providing a first operating voltage and a first clock frequency to a peripheral device, operating in a first operating state, wherein the peripheral device is coupled to an input-output (I/O) controller in a processing system with a serial bus;

monitoring bus transactions on the serial bus using a power manager, coupled between the I/O controller and the peripheral device, to assess a current processing demand for the peripheral device; and

dynamically adjusting at least one of the first operating voltage or the first clock frequency in response to the current processing demand, wherein a plurality of peripheral devices are coupled to the I/O controller using the power manager, including the peripheral device, and wherein the monitoring comprises;

receiving a start signal from the I/O controller for a current bus transaction;

decoding a device address of the current bus transaction to select one of the plurality of peripheral devices to send the current bus transaction;

delaying the current bus transaction from being sent to the selected peripheral device by placing the I/O controller in a wait state for the current bus transaction;

while delaying the current bus transaction, transitioning the selected peripheral device to a second operating state from the first operating state by said dynamically adjusting, wherein the first operating state is a lower power state than the second operating state;

initiating a device communication flow between the I/O controller and the peripheral device for the current bus transaction when the selected peripheral device is operating at the second operating state; and

determining that the selected peripheral device is a serial peripheral interface (SPI) device, and wherein initiating the device communication flow comprises;

asserting a chip select (CS) signal to the SPI device;

releasing the clock line between the I/O controller and the power manager to activate the I/O controller from the wait state; and

determining whether the current bus transaction is a read operation or a write operation, wherein if the current bus transaction is a read operation, the determining comprises;

holding the clock line between the I/O controller and the power manager low;

reading a first set of one or more bits of data from SPI device;

releasing the clock line between the I/O controller and the power manager; and

sending the first set of data to the I/O controller, and

wherein if the current bus transaction is a write operation, the determining comprises;

buffering a second set of one or more bits of data received from the I/O controller;

acknowledging the I/O controller;

holding the clock line between the I/O controller and the power manager low;

sending the second set of data received from the I/O controller to the SPI device; and

releasing the clock line between the I/O controller and the power manager.