Semiconductor chip manufacturing method

• US 8,314,013 B2
• Filed: 04/19/2010
• Issued: 11/20/2012
• Est. Priority Date: 03/12/2002
• Status: Expired due to Term

• Current Assignee: Hamamatsu Photonics KK
• Original Assignee: Hamamatsu Photonics KK
• Inventors: Fujii, Yoshimaro, Fukuyo, Fumitsugu, Fukumitsu, Kenshi, Uchiyama, Naoki
• Primary Examiner(s): Reames, Matthew
• Assistant Examiner(s): Ullah, Elias
• Application Number:
  US12/762,444
• Publication Number:
  US 20100203707A1
• Time in Patent Office: 946 Days
• Field of Search: 438460-463, 438/465, 257/E21.237
• US Class Current: 438/460
• CPC Class Codes: B23K 2103/50 Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26
• CPC Class Codes: B23K 26/0622 by shaping pulses
• CPC Class Codes: B23K 26/40 taking account of the properties of the material involved
• CPC Class Codes: B23K 26/53 for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
• CPC Class Codes: B28D 5/00 Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor working by grinding or polishing B24; for artistic purposes B44B
• CPC Class Codes: B28D 5/0011 with preliminary treatment, e.g. weakening by scoring
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76894 using a laser, e.g. laser cutting, laser direct writing, laser repair
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68336 involving stretching of the auxiliary support post dicing
• CPC Class Codes: H01L 2223/5446 Located in scribe lines
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness.

Claims

1. A semiconductor chip manufacturing method wherein a semiconductor substrate having a plurality of functional devices formed in a matrix on its front face is divided into the functional devices to obtain semiconductor chips, the method comprising the steps of:

irradiating a substrate with laser light, thereby forming a modified region embedded within the substrate along each line of a plurality of cutting lines arranged in a grid running betweeen the functional devices which are adjacent to one another; and

grinding or etching a rear face of the substrate after forming the modified regions, thereby causing the substrate to attain a predetermined thickness;

wherein after forming the modified regions and before grinding or etching the rear face of the substrate, fractures generated from each modified region reach the front face of the substrate.

2. A semiconductor chip manufacturing method according to claim 1, wherein after forming the modified regions and before grinding or etching the rear face of the substrate, the fractures separate the functional devices from each other.

3. A semiconductor chip manufacturing method according to claim 2, wherein the step of grinding or etching the rear face of the substrate includes a step of grinding or etching the rear face of the substrate so that the modified regions remain within the substrate.

4. A semiconductor chip manufacturing method according to claim 2, wherein the step of grinding or etching the rear thee of the substrate includes a step of grinding or etching the rear face of the substrate so that the modified regions do not remain within the substrate.

5. A semiconductor chip manufacturing method according to claim 1, wherein the step of grinding or etching the rear face of the substrate includes a step of grinding or etching the rear face of the substrate so that the modified regions remain within the substrate.

6. A semiconductor chip manufacturing method according to claim 1, wherein the step of grinding or etching the rear face of the substrate includes a step of grinding or etching the rear face of the substrate so that the modified regions do not remain within the substrate.