Memory reallocation and sharing in electronic systems

• US 8,321,636 B2
• Filed: 03/06/2006
• Issued: 11/27/2012
• Est. Priority Date: 09/02/2003
• Status: Expired due to Term

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Inventors: Vantalon, Nicolas P., Protic, Vojislav, Gronemeyer, Steven A.
• Primary Examiner(s): Campos, Yaima
• Assistant Examiner(s): DILLON, SAMUEL A
• Application Number:
  US11/369,898
• Publication Number:
  US 20060248289A1
• Time in Patent Office: 2,458 Days
• Field of Search: 711/147, 711/153, 710/104, 710/306, 710/308
• US Class Current: 711/147
• CPC Class Codes: G01S 19/215 issues related to spoofing
• CPC Class Codes: G01S 19/246 involving long acquisition integration times, extended snapshots of signals or methods specifically directed towards weak signal acquisition
• CPC Class Codes: G01S 19/29 carrier including Doppler, related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes
• CPC Class Codes: H04B 1/7075 with code phase acquisition
• CPC Class Codes: H04B 1/7097 Interference-related aspects
• CPC Class Codes: H04B 1/7107 Subtractive interference cancellation
• CPC Class Codes: H04B 2201/70715 with application-specific features

Abstract

Memory reallocation and sharing among components of an electronic system is provided. The electronic system includes a first memory area coupled for access by a first processor via a first bus, and a second memory area coupled for access by a second processor via a second bus. An example system includes a central processor as the first processor and a digital signal processor as the second processor. The electronic system further includes memory configurations that support shared access of the second memory area by the first processor. Using shared access, the first processor can directly access the second memory via the first bus or indirectly access the second memory via the second bus and the second processor. The memory sharing also includes partitioning the shared memory to simultaneously provide the first processor with direct and indirect access to the shared memory.

Claims

1. An electronic system comprising:

a first memory area coupled for access by a first processor via a first bus, the first bus having a plurality of bus sections separately branching from the first processor, wherein each bus section has a first end connected to the first processor and a second end opposite the first end, wherein the second end of one bus section is connected to the first memory area, and the second end of at least one other bus section bypasses and so is not connected to the first memory area;

a second memory area coupled for access by a second processor;

a second bus, the second bus having a first portion connected to the second processor for providing access to the second memory area via the second processor and a second portion connected to the second end of the at least one other bus section of the first bus that bypasses the first memory area;

at least one memory configuration that supports shared access of the second memory area by the first and second processors, wherein the at least one configuration includes access by the first processor to a first set of memory locations of the second memory area via the second processor and the at least one other bus section of the first bus that bypasses the first memory area, and access by the second processor to a second separate set of memory locations of the second memory area; and

at least one other memory configuration that supports direct access of the second memory area by the first processor and not via the second processor.

2. The system of claim 1, wherein the first processor is a central processor running in a first clock domain and the second processor is a digital signal processor (DSP) running in a second clock domain.

3. The system of claim 1, further comprising at least one decoder coupled to receive information on the first bus, wherein the at least one decoder uses at least one address of the information to select access to the first and the second memory areas.

4. The system of claim 3, wherein the at least one decoder selects the first memory area for access by data having an address in a first address range.

5. The system of claim 4, wherein the at least one decoder selects the second set of memory locations of the second memory area for access by data having an address in a second address range.

6. The system of claim 5, wherein the at least one decoder selects the first set of memory locations of the second memory area for access by data having an address in a third address range, wherein the third address range is a first subset of addresses of the second address range.

7. The system of claim 6, wherein the at least one decoder selects the first set of memory locations of the second memory area for access by data having an address in a fourth address range, wherein the fourth address range is a second subset of addresses of the second address range.

8. The system of claim 1, further comprising at least one configuration register that stores information including at least one memory configuration.

9. The system of claim 1, wherein the at least one memory configuration allows the first set of memory locations to be accessed at a speed associated with a clock speed of the first processor.

10. The system of claim 9, wherein the at least one memory configuration allows the second set of memory locations to be accessed at a speed associated with a clock speed of the second processor, wherein the clock speed of the first processor and the clock speed of the second processor are different.

11. The system of claim 1, further comprising at least one bridge unit that couples the first bus and the second bus, wherein access by the first processor to the second set of memory locations of the second memory area via the second bus includes mapping the second set of memory locations to the first memory area through the at least one bridge unit.

12. The system of claim 1, further comprising at least one memory interface that couples to the first bus and the second memory area, wherein access by the first processor to the first set of memory locations of the second memory area via the first bus includes mapping the first set of memory locations to the first memory through the at least one memory interface.

13. The system of claim 1, wherein the system is at least one of portable communication devices, portable position tracking devices, cellular telephones, cellular telephones coupled to position tracking devices, cellular telephones including position tracking devices, mobile electronic devices, mobile communication devices, personal digital assistants, and processor-based devices.

14. The system of claim 1, wherein the at least one memory configuration allows the first set of memory locations to be accessed at a speed associated with a clock speed of the second processor that is different from a clock speed of the first processor.

15. The system of claim 1, wherein the at least one memory configuration allows the first set of memory locations to be indirectly accessed by the first processor using no soft mapping of memory addresses of the second processor.

16. The system of claim 1, wherein the at least one memory configuration allows the first set of memory locations to be indirectly accessed by the processor through soft mapping of memory addresses of the second processor.

17. An electronic system for reallocation and sharing of memory among a plurality of processors in an embedded device, the system comprising:

a first processor;

a first bus having a plurality of bus sections separately branching from the first processor, each bus section having a first end connected to the first processor and a second end opposite the first end;

a second processor;

a second bus having a first portion connected to the second processor;

a memory area coupled to the second processor, and configured to be accessed via the second processor, wherein the memory area has a first and a second set of memory locations configured to be accessed via the second processor;

a bridge circuit for coupling a second portion of the second bus to the second end of one of the plurality of bus sections of the first bus; and

a memory configuration circuit that supports shared access of the memory area by the first processor and the second processor, wherein the memory configuration circuit controls access by the first processor to the first set of memory locations via the second processor and the one of the plurality of bus sections of the first bus, and access by the second processor to the second set of memory locations, and wherein the memory configuration circuit further controls direct access of the memory area by the first processor and not via the second processor.

18. The system of claim 17, wherein the system is at least one of portable communication devices, portable position tracking devices, cellular telephones, cellular telephones coupled to position tracking devices, cellular telephones including position tracking devices, mobile electronic devices, mobile communication devices, personal digital assistants, and processor-based devices.