Package system with a shielded inverted internal stacking module and method of manufacture thereof

• US 8,334,171 B2
• Filed: 12/02/2009
• Issued: 12/18/2012
• Est. Priority Date: 12/02/2009
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Pagaila, Reza Argenty, Camacho, Zigmund Ramirez, Bathan, Henry Descalzo
• Primary Examiner(s): Ingham, John C
• Application Number:
  US12/629,877
• Publication Number:
  US 20110127653A1
• Time in Patent Office: 1,112 Days
• Field of Search: 438/109, 257/659, 257/686, 257/E25.013, 257/E23.085, 257/E23.13, 257/E23.114
• US Class Current: 438/109
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A method of manufacture of a package system includes: providing a base package substrate having conductive elements; providing an internal stacking module having a semiconductor die mounted on a package substrate and a first encapsulant surrounding at least portions of the semiconductor die and the package substrate; covering at least portions of the first encapsulant in the internal stacking module with an electromagnetic interference shield, the electromagnetic interference shield shaped to have an outside face; mounting the internal stacking module over the base package substrate with the outside face of the electromagnetic interference shield facing the base package substrate; and encapsulating at least portions of the internal stacking module, the electromagnetic interference shield, and the base package substrate using a second encapsulant.

Claims

1. A method of manufacture of a package system comprising:

providing a base package substrate having conductive elements;

providing an internal stacking module having a semiconductor die mounted on a package substrate and a first encapsulant surrounding at least portions of the semiconductor die and the package substrate;

attaching an electromagnetic interference shield to the first encapsulant, the electromagnetic interference shield covering vertical sides of the first encapsulant and a side of the first encapsulant opposite the package substrate, the electromagnetic interference shield shaped to have an outside face and structurally isolated from a vertical side of the package substrate;

mounting the internal stacking module over the base package substrate with the outside face of the electromagnetic interference shield facing the base package substrate; and

encapsulating at least portions of the internal stacking module, the electromagnetic interference shield, and the base package substrate using a second encapsulant.

2. The method as claimed in claim 1 further comprising connecting the electromagnetic interference shield to the conductive elements in the base package substrate using interconnects arranged between the electromagnetic interference shield and the conductive elements in the base package substrate.

3. The method as claimed in claim 1 wherein the base package substrate is a leadframe having a die paddle, and further comprising connecting the outside face of the electromagnetic interference shield to the die paddle in the leadframe using a conductive layer.

4. The method as claimed in claim 1 wherein the electromagnetic interference shield is formed using a conductive layer with a fillet configured to cover the sides of the internal stacking module.

5. The method as claimed in claim 1 further comprising mounting a second semiconductor die on the package substrate.

6. A method of manufacture of a package system comprising:

providing a base package substrate having conductive elements;

providing an internal stacking module having a semiconductor die mounted on a package substrate and a first encapsulant surrounding at least portions of the semiconductor die and the package substrate;

attaching an electromagnetic interference shield to the first encapsulant, the electromagnetic interference shield covering vertical sides of the first encapsulant and a side of the first encapsulant opposite the package substrate, the electromagnetic interference shield shaped to have an outside face and structurally isolated from a vertical side of the package substrate;

mounting the internal stacking module over the base package substrate with the outside face of the electromagnetic interference shield facing the base package substrate;

mounting a second semiconductor die over the base package substrate; and

encapsulating at least portions of the internal stacking module, the electromagnetic interference shield, the second semiconductor die, and the base package substrate using a second encapsulant.

7. The method as claimed in claim 6 wherein the second semiconductor die is mounted over the package substrate.

8. The method as claimed in claim 6 wherein the second semiconductor die is mounted between the internal stacking module and the base package substrate.

9. The method as claimed in claim 6 wherein the second semiconductor die is a silicon interposer having a through silicon via placed between the internal stacking module and the base package substrate.

10. The method as claimed in claim 6 further comprising a conductive bridge connecting the electromagnetic interference shield to conductive elements in the base package substrate.

11. A package system comprising:

a base package substrate having conductive elements;

an internal stacking module having a semiconductor die mounted on a package substrate and a first encapsulant surrounding at least portions of the semiconductor die and the package substrate;

an electromagnetic interference shield covering vertical sides of the first encapsulant and a side of the first encapsulant opposite the package substrate, the electromagnetic interference shield structurally isolated from a vertical side of the package substrate and shaped to have an outside face covering the first encapsulant in the internal stacking module with the outside face of the electromagnetic interference shield facing the base package substrate; and

a second encapsulant encapsulating at least portions of the internal stacking module, the electromagnetic interference shield, and the base package substrate.

12. The system as claimed in claim 11 further comprising interconnects for connecting the electromagnetic interference shield to the conductive elements in the base package substrate.

13. The system as claimed in claim 11 wherein the base package substrate is a leadframe having a die paddle, and further comprising a conductive layer for connecting the electromagnetic interference shield to the die paddle in the leadframe.

14. The system as claimed in claim 11 wherein the electromagnetic interference shield is a conductive layer with a fillet configured to cover the sides of the internal stacking module.

15. The system as claimed in claim 11 further comprising a second semiconductor die mounted on the package substrate.

16. The system as claimed in claim 11 further comprising a second semiconductor die mounted over the base package substrate.

17. The system as claimed in claim 16 wherein the second semiconductor die is located over the package substrate.

18. The system as claimed in claim 16 wherein the second semiconductor die is placed between the internal stacking module and the base package substrate.

19. The system as claimed in claim 16 wherein the second semiconductor die is a silicon interposer having a through silicon via.

20. The system as claimed in claim 16 further comprising a conductive bridge for connecting the electromagnetic interference shield to the conductive elements in the base package substrate.